+/* SPDX-License-Identifier: GPL-2.0+ */
/*
* (C) Copyright 2010-2014
* NVIDIA Corporation <www.nvidia.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
*/
#ifndef _TEGRA_PINMUX_H_
#define _TEGRA_PINMUX_H_
+#include <linux/types.h>
+
#include <asm/arch/tegra.h>
/* The pullup/pulldown state of a pin group */
void pinmux_config_pingrp_table(const struct pmux_pingrp_config *config,
int len);
+struct pmux_pingrp_desc {
+ u8 funcs[4];
+#if defined(CONFIG_TEGRA20)
+ u8 ctl_id;
+ u8 pull_id;
+#endif /* CONFIG_TEGRA20 */
+};
+
+extern const struct pmux_pingrp_desc *tegra_soc_pingroups;
+
#ifdef TEGRA_PMX_SOC_HAS_DRVGRPS
#define PMUX_SLWF_MIN 0
#endif /* TEGRA_PMX_SOC_HAS_DRVGRPS */
-struct pmux_pingrp_desc {
- u8 funcs[4];
-#if defined(CONFIG_TEGRA20)
- u8 ctl_id;
- u8 pull_id;
-#endif /* CONFIG_TEGRA20 */
+#ifdef TEGRA_PMX_SOC_HAS_MIPI_PAD_CTRL_GRPS
+struct pmux_mipipadctrlgrp_config {
+ u32 grp:16; /* pin group PMUX_MIPIPADCTRLGRP_x */
+ u32 func:8; /* function to assign PMUX_FUNC_... */
};
-extern const struct pmux_pingrp_desc *tegra_soc_pingroups;
+void pinmux_config_mipipadctrlgrp_table(
+ const struct pmux_mipipadctrlgrp_config *config, int len);
+
+struct pmux_mipipadctrlgrp_desc {
+ u8 funcs[2];
+};
+
+extern const struct pmux_mipipadctrlgrp_desc *tegra_soc_mipipadctrl_groups;
+#endif /* TEGRA_PMX_SOC_HAS_MIPI_PAD_CTRL_GRPS */
#endif /* _TEGRA_PINMUX_H_ */