ARM: stm32: fix stm32f7 sdram fmc base address

[platform/kernel/u-boot.git] / arch / arm / include / asm / arch-stm32f7 / stm32.h

diff --git a/arch/arm/include/asm/arch-stm32f7/stm32.h b/arch/arm/include/asm/arch-stm32f7/stm32.h
index 68bdab0..14e3398 100644 (file)
--- a/arch/arm/include/asm/arch-stm32f7/stm32.h
+++ b/arch/arm/include/asm/arch-stm32f7/stm32.h
@@ -32,6 +32,7 @@
 
 #define USART1_BASE            (APB2_PERIPH_BASE + 0x1000)
 #define USART6_BASE            (APB2_PERIPH_BASE + 0x1400)
+#define STM32_SYSCFG_BASE      (APB2_PERIPH_BASE + 0x3800)
 
 #define STM32_GPIOA_BASE       (AHB1_PERIPH_BASE + 0x0000)
 #define STM32_GPIOB_BASE       (AHB1_PERIPH_BASE + 0x0400)
@@ -48,7 +49,7 @@
 #define FLASH_CNTL_BASE                (AHB1_PERIPH_BASE + 0x3C00)
 
 
-#define SDRAM_FMC_BASE         (AHB3_PERIPH_BASE + 0x4A0000140)
+#define SDRAM_FMC_BASE         (AHB3_PERIPH_BASE + 0x40000140)
 
 static const u32 sect_sz_kb[CONFIG_SYS_MAX_FLASH_SECT] = {
        [0 ... 3] =     32 * 1024,
@@ -62,8 +63,59 @@ enum clock {
        CLOCK_APB1,
        CLOCK_APB2
 };
-#define STM32_BUS_MASK          0xFFFF0000
+#define STM32_BUS_MASK         GENMASK(31, 16)
+
+struct stm32_rcc_regs {
+       u32 cr;         /* RCC clock control */
+       u32 pllcfgr;    /* RCC PLL configuration */
+       u32 cfgr;       /* RCC clock configuration */
+       u32 cir;        /* RCC clock interrupt */
+       u32 ahb1rstr;   /* RCC AHB1 peripheral reset */
+       u32 ahb2rstr;   /* RCC AHB2 peripheral reset */
+       u32 ahb3rstr;   /* RCC AHB3 peripheral reset */
+       u32 rsv0;
+       u32 apb1rstr;   /* RCC APB1 peripheral reset */
+       u32 apb2rstr;   /* RCC APB2 peripheral reset */
+       u32 rsv1[2];
+       u32 ahb1enr;    /* RCC AHB1 peripheral clock enable */
+       u32 ahb2enr;    /* RCC AHB2 peripheral clock enable */
+       u32 ahb3enr;    /* RCC AHB3 peripheral clock enable */
+       u32 rsv2;
+       u32 apb1enr;    /* RCC APB1 peripheral clock enable */
+       u32 apb2enr;    /* RCC APB2 peripheral clock enable */
+       u32 rsv3[2];
+       u32 ahb1lpenr;  /* RCC AHB1 periph clk enable in low pwr mode */
+       u32 ahb2lpenr;  /* RCC AHB2 periph clk enable in low pwr mode */
+       u32 ahb3lpenr;  /* RCC AHB3 periph clk enable in low pwr mode */
+       u32 rsv4;
+       u32 apb1lpenr;  /* RCC APB1 periph clk enable in low pwr mode */
+       u32 apb2lpenr;  /* RCC APB2 periph clk enable in low pwr mode */
+       u32 rsv5[2];
+       u32 bdcr;       /* RCC Backup domain control */
+       u32 csr;        /* RCC clock control & status */
+       u32 rsv6[2];
+       u32 sscgr;      /* RCC spread spectrum clock generation */
+       u32 plli2scfgr; /* RCC PLLI2S configuration */
+       u32 pllsaicfgr; /* PLLSAI configuration */
+       u32 dckcfgr;    /* dedicated clocks configuration register */
+};
+#define STM32_RCC              ((struct stm32_rcc_regs *)RCC_BASE)
+
+struct stm32_rcc_ext_f7_regs {
+       u32 dckcfgr2;   /* dedicated clocks configuration register */
+};
+#define STM32_RCC_EXT_F7       ((struct stm32_rcc_ext_f7_regs *) (RCC_BASE + sizeof(struct stm32_rcc_regs)))
+
+struct stm32_pwr_regs {
+       u32 cr1;   /* power control register 1 */
+       u32 csr1;  /* power control/status register 2 */
+       u32 cr2;   /* power control register 2 */
+       u32 csr2;  /* power control/status register 2 */
+};
+#define STM32_PWR              ((struct stm32_pwr_regs *)PWR_BASE)
 
 int configure_clocks(void);
+unsigned long clock_get(enum clock clck);
+void stm32_flash_latency_cfg(int latency);
 
 #endif /* _ASM_ARCH_HARDWARE_H */