ARM: stm32: fix stm32f7 sdram fmc base address

[platform/kernel/u-boot.git] / arch / arm / include / asm / arch-stm32f7 / rcc.h

diff --git a/arch/arm/include/asm/arch-stm32f7/rcc.h b/arch/arm/include/asm/arch-stm32f7/rcc.h
index 8bfb7b6..184c366 100644 (file)
--- a/arch/arm/include/asm/arch-stm32f7/rcc.h
+++ b/arch/arm/include/asm/arch-stm32f7/rcc.h
@@ -34,31 +34,43 @@
 #define RCC_PLLSAICFG  0x88    /* PLLSAI configuration */
 #define RCC_DCKCFG1    0x8C    /* dedicated clocks configuration register */
 #define RCC_DCKCFG2    0x90    /* dedicated clocks configuration register */
+/*
+ * RCC AHB1ENR specific definitions
+ */
+#define RCC_AHB1ENR_GPIO_A_EN          BIT(0)
+#define RCC_AHB1ENR_GPIO_B_EN          BIT(1)
+#define RCC_AHB1ENR_GPIO_C_EN          BIT(2)
+#define RCC_AHB1ENR_GPIO_D_EN          BIT(3)
+#define RCC_AHB1ENR_GPIO_E_EN          BIT(4)
+#define RCC_AHB1ENR_GPIO_F_EN          BIT(5)
+#define RCC_AHB1ENR_GPIO_G_EN          BIT(6)
+#define RCC_AHB1ENR_GPIO_H_EN          BIT(7)
+#define RCC_AHB1ENR_GPIO_I_EN          BIT(8)
+#define RCC_AHB1ENR_GPIO_J_EN          BIT(9)
+#define RCC_AHB1ENR_GPIO_K_EN          BIT(10)
+#define RCC_AHB1ENR_ETHMAC_EN          BIT(25)
+#define RCC_AHB1ENR_ETHMAC_TX_EN       BIT(26)
+#define RCC_AHB1ENR_ETHMAC_RX_EN       BIT(27)
+#define RCC_AHB1ENR_ETHMAC_PTP_EN      BIT(28)
 
-#define RCC_APB1ENR_TIM2EN             (1 << 0)
-#define RCC_APB1ENR_PWREN              (1 << 28)
+/*
+ * RCC AHB3ENR specific definitions
+ */
+#define RCC_AHB3ENR_FMC_EN             BIT(0)
 
 /*
- * RCC USART specific definitions
+ * RCC APB1ENR specific definitions
  */
-#define RCC_ENR_USART1EN               (1 << 4)
-#define RCC_ENR_USART2EN               (1 << 17)
-#define RCC_ENR_USART3EN               (1 << 18)
-#define RCC_ENR_USART6EN               (1 <<  5)
+#define RCC_APB1ENR_TIM2EN             BIT(0)
+#define RCC_APB1ENR_USART2EN           BIT(17)
+#define RCC_APB1ENR_USART3EN           BIT(18)
+#define RCC_APB1ENR_PWREN              BIT(28)
 
 /*
- * RCC GPIO specific definitions
+ * RCC APB2ENR specific definitions
  */
-#define RCC_ENR_GPIO_A_EN              (1 << 0)
-#define RCC_ENR_GPIO_B_EN              (1 << 1)
-#define RCC_ENR_GPIO_C_EN              (1 << 2)
-#define RCC_ENR_GPIO_D_EN              (1 << 3)
-#define RCC_ENR_GPIO_E_EN              (1 << 4)
-#define RCC_ENR_GPIO_F_EN              (1 << 5)
-#define RCC_ENR_GPIO_G_EN              (1 << 6)
-#define RCC_ENR_GPIO_H_EN              (1 << 7)
-#define RCC_ENR_GPIO_I_EN              (1 << 8)
-#define RCC_ENR_GPIO_J_EN              (1 << 9)
-#define RCC_ENR_GPIO_K_EN              (1 << 10)
+#define RCC_APB2ENR_USART1EN           BIT(4)
+#define RCC_APB2ENR_USART6EN           BIT(5)
+#define RCC_APB2ENR_SYSCFGEN           BIT(14)
 
 #endif