(struct gpt_regs *)TIM2_BASE;
/* Timer control1 register */
-#define GPT_CR1_CEN 0x0001
-#define GPT_MODE_AUTO_RELOAD (1 << 7)
+#define GPT_CR1_CEN BIT(0)
+#define GPT_MODE_AUTO_RELOAD BIT(7)
/* Auto reload register for free running config */
#define GPT_FREE_RUNNING 0xFFFFFFFF
#define CONFIG_STM32_HZ 1000
/* Timer Event Generation registers */
-#define TIM_EGR_UG (1 << 0)
+#define TIM_EGR_UG BIT(0)
#endif