#define ANA_APB_ARM_MF_REG (ANA_REGS_GLB_PHYS + 0x110)
#define ANA_APB_AFUSE_CTL (ANA_REGS_GLB_PHYS + 0x114)
#define ANA_APB_AFUSE_OUT0 (ANA_REGS_GLB_PHYS + 0x118)
-#define ANA_APB_AFUSE_OUT0 (ANA_REGS_GLB_PHYS + 0x11C)
-#define ANA_APB_AFUSE_OUT0 (ANA_REGS_GLB_PHYS + 0x120)
-#define ANA_APB_AFUSE_OUT0 (ANA_REGS_GLB_PHYS + 0x124)
+#define ANA_APB_AFUSE_OUT1 (ANA_REGS_GLB_PHYS + 0x11C)
+#define ANA_APB_AFUSE_OUT2 (ANA_REGS_GLB_PHYS + 0x120)
+#define ANA_APB_AFUSE_OUT3 (ANA_REGS_GLB_PHYS + 0x124)
#define ANA_APB_ARCH_EN (ANA_REGS_GLB_PHYS + 0x128)
#define ANA_APB_MCU_WR_PROT_VAL (ANA_REGS_GLB_PHYS + 0x12C)
#define ANA_APB_DCDC_CORE (ANA_REGS_GLB_PHYS + 0x160)