GRF_GPIO2C1_SEL_SHIFT = 2,
GRF_GPIO2C1_SEL_MASK = 3 << GRF_GPIO2C1_SEL_SHIFT,
GRF_UART0BT_SOUT = 1,
+ GRF_GPIO2C4_SEL_SHIFT = 8,
+ GRF_GPIO2C4_SEL_MASK = 3 << GRF_GPIO2C4_SEL_SHIFT,
+ GRF_SPI5EXPPLUS_RXD = 2,
+ GRF_GPIO2C5_SEL_SHIFT = 10,
+ GRF_GPIO2C5_SEL_MASK = 3 << GRF_GPIO2C5_SEL_SHIFT,
+ GRF_SPI5EXPPLUS_TXD = 2,
+ GRF_GPIO2C6_SEL_SHIFT = 12,
+ GRF_GPIO2C6_SEL_MASK = 3 << GRF_GPIO2C6_SEL_SHIFT,
+ GRF_SPI5EXPPLUS_CLK = 2,
+ GRF_GPIO2C7_SEL_SHIFT = 14,
+ GRF_GPIO2C7_SEL_MASK = 3 << GRF_GPIO2C7_SEL_SHIFT,
+ GRF_SPI5EXPPLUS_CSN0 = 2,
/* GRF_GPIO3A_IOMUX */
GRF_GPIO3A0_SEL_SHIFT = 0,