};
u32 gpio4d_iomux;
u32 reserved21[4];
- u32 gpio2_p[3][4];
+ u32 gpio2_p[4];
+ u32 gpio3_p[4];
+ u32 gpio4_p[4];
u32 reserved22[4];
u32 gpio2_sr[3][4];
u32 reserved23[4];
u32 gpio2_smt[3][4];
- u32 reserved24[(0xe130 - 0xe0ec)/4 - 1];
- u32 gpio4b_e01;
- u32 gpio4b_e2;
- u32 reserved24a[(0xe200 - 0xe134)/4 - 1];
+ u32 reserved24[(0xe100 - 0xe0ec)/4 - 1];
+ u32 gpio2_e[4];
+ u32 gpio3_e[7];
+ u32 gpio4_e[5];
+ u32 reserved24a[(0xe200 - 0xe13c)/4 - 1];
u32 soc_con0;
u32 soc_con1;
u32 soc_con2;
};
u32 gpio1d_iomux;
u32 reserved1[8];
- u32 gpio0_p[2][4];
+ u32 gpio0_p[2];
+ u32 reserved2[2];
+ u32 gpio1_p[4];
u32 reserved3[8];
u32 gpio0a_e;
u32 reserved4;
GRF_GPIO2B4_SEL_MASK = 3 << GRF_GPIO2B4_SEL_SHIFT,
GRF_SPI2TPM_CSN0 = 1,
+ /* GRF_GPIO2C_IOMUX */
+ GRF_GPIO2C0_SEL_SHIFT = 0,
+ GRF_GPIO2C0_SEL_MASK = 3 << GRF_GPIO2C0_SEL_SHIFT,
+ GRF_UART0BT_SIN = 1,
+ GRF_GPIO2C1_SEL_SHIFT = 2,
+ GRF_GPIO2C1_SEL_MASK = 3 << GRF_GPIO2C1_SEL_SHIFT,
+ GRF_UART0BT_SOUT = 1,
+ GRF_GPIO2C4_SEL_SHIFT = 8,
+ GRF_GPIO2C4_SEL_MASK = 3 << GRF_GPIO2C4_SEL_SHIFT,
+ GRF_SPI5EXPPLUS_RXD = 2,
+ GRF_GPIO2C5_SEL_SHIFT = 10,
+ GRF_GPIO2C5_SEL_MASK = 3 << GRF_GPIO2C5_SEL_SHIFT,
+ GRF_SPI5EXPPLUS_TXD = 2,
+ GRF_GPIO2C6_SEL_SHIFT = 12,
+ GRF_GPIO2C6_SEL_MASK = 3 << GRF_GPIO2C6_SEL_SHIFT,
+ GRF_SPI5EXPPLUS_CLK = 2,
+ GRF_GPIO2C7_SEL_SHIFT = 14,
+ GRF_GPIO2C7_SEL_MASK = 3 << GRF_GPIO2C7_SEL_SHIFT,
+ GRF_SPI5EXPPLUS_CSN0 = 2,
+
/* GRF_GPIO3A_IOMUX */
+ GRF_GPIO3A0_SEL_SHIFT = 0,
+ GRF_GPIO3A0_SEL_MASK = 3 << GRF_GPIO3A0_SEL_SHIFT,
+ GRF_MAC_TXD2 = 1,
+ GRF_GPIO3A1_SEL_SHIFT = 2,
+ GRF_GPIO3A1_SEL_MASK = 3 << GRF_GPIO3A1_SEL_SHIFT,
+ GRF_MAC_TXD3 = 1,
+ GRF_GPIO3A2_SEL_SHIFT = 4,
+ GRF_GPIO3A2_SEL_MASK = 3 << GRF_GPIO3A2_SEL_SHIFT,
+ GRF_MAC_RXD2 = 1,
+ GRF_GPIO3A3_SEL_SHIFT = 6,
+ GRF_GPIO3A3_SEL_MASK = 3 << GRF_GPIO3A3_SEL_SHIFT,
+ GRF_MAC_RXD3 = 1,
GRF_GPIO3A4_SEL_SHIFT = 8,
GRF_GPIO3A4_SEL_MASK = 3 << GRF_GPIO3A4_SEL_SHIFT,
+ GRF_MAC_TXD0 = 1,
GRF_SPI0NORCODEC_RXD = 2,
GRF_GPIO3A5_SEL_SHIFT = 10,
GRF_GPIO3A5_SEL_MASK = 3 << GRF_GPIO3A5_SEL_SHIFT,
+ GRF_MAC_TXD1 = 1,
GRF_SPI0NORCODEC_TXD = 2,
GRF_GPIO3A6_SEL_SHIFT = 12,
GRF_GPIO3A6_SEL_MASK = 3 << GRF_GPIO3A6_SEL_SHIFT,
+ GRF_MAC_RXD0 = 1,
GRF_SPI0NORCODEC_CLK = 2,
GRF_GPIO3A7_SEL_SHIFT = 14,
GRF_GPIO3A7_SEL_MASK = 3 << GRF_GPIO3A7_SEL_SHIFT,
+ GRF_MAC_RXD1 = 1,
GRF_SPI0NORCODEC_CSN0 = 2,
/* GRF_GPIO3B_IOMUX */
GRF_GPIO3B0_SEL_SHIFT = 0,
GRF_GPIO3B0_SEL_MASK = 3 << GRF_GPIO3B0_SEL_SHIFT,
+ GRF_MAC_MDC = 1,
GRF_SPI0NORCODEC_CSN1 = 2,
+ GRF_GPIO3B1_SEL_SHIFT = 2,
+ GRF_GPIO3B1_SEL_MASK = 3 << GRF_GPIO3B1_SEL_SHIFT,
+ GRF_MAC_RXDV = 1,
+ GRF_GPIO3B3_SEL_SHIFT = 6,
+ GRF_GPIO3B3_SEL_MASK = 3 << GRF_GPIO3B3_SEL_SHIFT,
+ GRF_MAC_CLK = 1,
+ GRF_GPIO3B4_SEL_SHIFT = 8,
+ GRF_GPIO3B4_SEL_MASK = 3 << GRF_GPIO3B4_SEL_SHIFT,
+ GRF_MAC_TXEN = 1,
+ GRF_GPIO3B5_SEL_SHIFT = 10,
+ GRF_GPIO3B5_SEL_MASK = 3 << GRF_GPIO3B5_SEL_SHIFT,
+ GRF_MAC_MDIO = 1,
+ GRF_GPIO3B6_SEL_SHIFT = 12,
+ GRF_GPIO3B6_SEL_MASK = 3 << GRF_GPIO3B6_SEL_SHIFT,
+ GRF_MAC_RXCLK = 1,
+
+ /* GRF_GPIO3C_IOMUX */
+ GRF_GPIO3C1_SEL_SHIFT = 2,
+ GRF_GPIO3C1_SEL_MASK = 3 << GRF_GPIO3C1_SEL_SHIFT,
+ GRF_MAC_TXCLK = 1,
/* GRF_GPIO4B_IOMUX */
GRF_GPIO4B0_SEL_SHIFT = 0,
GRF_GPIO4C0_SEL_SHIFT = 0,
GRF_GPIO4C0_SEL_MASK = 3 << GRF_GPIO4C0_SEL_SHIFT,
GRF_UART2DGBB_SIN = 2,
+ GRF_HDMII2C_SCL = 3,
GRF_GPIO4C1_SEL_SHIFT = 2,
GRF_GPIO4C1_SEL_MASK = 3 << GRF_GPIO4C1_SEL_SHIFT,
GRF_UART2DGBB_SOUT = 2,
+ GRF_HDMII2C_SDA = 3,
GRF_GPIO4C2_SEL_SHIFT = 4,
GRF_GPIO4C2_SEL_MASK = 3 << GRF_GPIO4C2_SEL_SHIFT,
GRF_PWM_0 = 1,
GRF_GPIO4C6_SEL_MASK = 3 << GRF_GPIO4C6_SEL_SHIFT,
GRF_PWM_1 = 1,
+ /* GRF_GPIO3A_E01 */
+ GRF_GPIO3A0_E_SHIFT = 0,
+ GRF_GPIO3A0_E_MASK = 7 << GRF_GPIO3A0_E_SHIFT,
+ GRF_GPIO3A1_E_SHIFT = 3,
+ GRF_GPIO3A1_E_MASK = 7 << GRF_GPIO3A1_E_SHIFT,
+ GRF_GPIO3A2_E_SHIFT = 6,
+ GRF_GPIO3A2_E_MASK = 7 << GRF_GPIO3A2_E_SHIFT,
+ GRF_GPIO3A3_E_SHIFT = 9,
+ GRF_GPIO3A3_E_MASK = 7 << GRF_GPIO3A3_E_SHIFT,
+ GRF_GPIO3A4_E_SHIFT = 12,
+ GRF_GPIO3A4_E_MASK = 7 << GRF_GPIO3A4_E_SHIFT,
+ GRF_GPIO3A5_E0_SHIFT = 15,
+ GRF_GPIO3A5_E0_MASK = 1 << GRF_GPIO3A5_E0_SHIFT,
+
+ /* GRF_GPIO3A_E2 */
+ GRF_GPIO3A5_E12_SHIFT = 0,
+ GRF_GPIO3A5_E12_MASK = 3 << GRF_GPIO3A5_E12_SHIFT,
+ GRF_GPIO3A6_E_SHIFT = 2,
+ GRF_GPIO3A6_E_MASK = 7 << GRF_GPIO3A6_E_SHIFT,
+ GRF_GPIO3A7_E_SHIFT = 5,
+ GRF_GPIO3A7_E_MASK = 7 << GRF_GPIO3A7_E_SHIFT,
+
+ /* GRF_GPIO3B_E01 */
+ GRF_GPIO3B0_E_SHIFT = 0,
+ GRF_GPIO3B0_E_MASK = 7 << GRF_GPIO3B0_E_SHIFT,
+ GRF_GPIO3B1_E_SHIFT = 3,
+ GRF_GPIO3B1_E_MASK = 7 << GRF_GPIO3B1_E_SHIFT,
+ GRF_GPIO3B2_E_SHIFT = 6,
+ GRF_GPIO3B2_E_MASK = 7 << GRF_GPIO3B2_E_SHIFT,
+ GRF_GPIO3B3_E_SHIFT = 9,
+ GRF_GPIO3B3_E_MASK = 7 << GRF_GPIO3B3_E_SHIFT,
+ GRF_GPIO3B4_E_SHIFT = 12,
+ GRF_GPIO3B4_E_MASK = 7 << GRF_GPIO3B4_E_SHIFT,
+ GRF_GPIO3B5_E0_SHIFT = 15,
+ GRF_GPIO3B5_E0_MASK = 1 << GRF_GPIO3B5_E0_SHIFT,
+
+ /* GRF_GPIO3A_E2 */
+ GRF_GPIO3B5_E12_SHIFT = 0,
+ GRF_GPIO3B5_E12_MASK = 3 << GRF_GPIO3B5_E12_SHIFT,
+ GRF_GPIO3B6_E_SHIFT = 2,
+ GRF_GPIO3B6_E_MASK = 7 << GRF_GPIO3B6_E_SHIFT,
+ GRF_GPIO3B7_E_SHIFT = 5,
+ GRF_GPIO3B7_E_MASK = 7 << GRF_GPIO3B7_E_SHIFT,
+
+ /* GRF_GPIO3C_E01 */
+ GRF_GPIO3C0_E_SHIFT = 0,
+ GRF_GPIO3C0_E_MASK = 7 << GRF_GPIO3C0_E_SHIFT,
+ GRF_GPIO3C1_E_SHIFT = 3,
+ GRF_GPIO3C1_E_MASK = 7 << GRF_GPIO3C1_E_SHIFT,
+ GRF_GPIO3C2_E_SHIFT = 6,
+ GRF_GPIO3C2_E_MASK = 7 << GRF_GPIO3C2_E_SHIFT,
+ GRF_GPIO3C3_E_SHIFT = 9,
+ GRF_GPIO3C3_E_MASK = 7 << GRF_GPIO3C3_E_SHIFT,
+ GRF_GPIO3C4_E_SHIFT = 12,
+ GRF_GPIO3C4_E_MASK = 7 << GRF_GPIO3C4_E_SHIFT,
+ GRF_GPIO3C5_E0_SHIFT = 15,
+ GRF_GPIO3C5_E0_MASK = 1 << GRF_GPIO3C5_E0_SHIFT,
+
+ /* GRF_GPIO3C_E2 */
+ GRF_GPIO3C5_E12_SHIFT = 0,
+ GRF_GPIO3C5_E12_MASK = 3 << GRF_GPIO3C5_E12_SHIFT,
+ GRF_GPIO3C6_E_SHIFT = 2,
+ GRF_GPIO3C6_E_MASK = 7 << GRF_GPIO3C6_E_SHIFT,
+ GRF_GPIO3C7_E_SHIFT = 5,
+ GRF_GPIO3C7_E_MASK = 7 << GRF_GPIO3C7_E_SHIFT,
+
/* GRF_SOC_CON7 */
- GRF_UART_DBG_SEL_SHIFT = 10,
- GRF_UART_DBG_SEL_MASK = 3 << GRF_UART_DBG_SEL_SHIFT,
- GRF_UART_DBG_SEL_C = 2,
+ GRF_UART_DBG_SEL_SHIFT = 10,
+ GRF_UART_DBG_SEL_MASK = 3 << GRF_UART_DBG_SEL_SHIFT,
+ GRF_UART_DBG_SEL_C = 2,
+
+ /* GRF_SOC_CON20 */
+ GRF_DSI0_VOP_SEL_SHIFT = 0,
+ GRF_DSI0_VOP_SEL_MASK = 1 << GRF_DSI0_VOP_SEL_SHIFT,
+ GRF_DSI0_VOP_SEL_B = 0,
+ GRF_DSI0_VOP_SEL_L = 1,
+ GRF_RK3399_HDMI_VOP_SEL_MASK = 1 << 6,
+ GRF_RK3399_HDMI_VOP_SEL_B = 0 << 6,
+ GRF_RK3399_HDMI_VOP_SEL_L = 1 << 6,
+
+ /* GRF_SOC_CON22 */
+ GRF_DPHY_TX0_RXMODE_SHIFT = 0,
+ GRF_DPHY_TX0_RXMODE_MASK = 0xf << GRF_DPHY_TX0_RXMODE_SHIFT,
+ GRF_DPHY_TX0_RXMODE_EN = 0xb,
+ GRF_DPHY_TX0_RXMODE_DIS = 0,
+
+ GRF_DPHY_TX0_TXSTOPMODE_SHIFT = 4,
+ GRF_DPHY_TX0_TXSTOPMODE_MASK = 0xf0 << GRF_DPHY_TX0_TXSTOPMODE_SHIFT,
+ GRF_DPHY_TX0_TXSTOPMODE_EN = 0xc,
+ GRF_DPHY_TX0_TXSTOPMODE_DIS = 0,
+
+ GRF_DPHY_TX0_TURNREQUEST_SHIFT = 12,
+ GRF_DPHY_TX0_TURNREQUEST_MASK =
+ 0xf000 << GRF_DPHY_TX0_TURNREQUEST_SHIFT,
+ GRF_DPHY_TX0_TURNREQUEST_EN = 0x1,
+ GRF_DPHY_TX0_TURNREQUEST_DIS = 0,
/* PMUGRF_GPIO0A_IOMUX */
PMUGRF_GPIO0A6_SEL_SHIFT = 12,
};
+/* GRF_SOC_CON5 */
+enum {
+ RK3399_GMAC_PHY_INTF_SEL_SHIFT = 9,
+ RK3399_GMAC_PHY_INTF_SEL_MASK = (7 << RK3399_GMAC_PHY_INTF_SEL_SHIFT),
+ RK3399_GMAC_PHY_INTF_SEL_RGMII = (1 << RK3399_GMAC_PHY_INTF_SEL_SHIFT),
+ RK3399_GMAC_PHY_INTF_SEL_RMII = (4 << RK3399_GMAC_PHY_INTF_SEL_SHIFT),
+
+ RK3399_GMAC_CLK_SEL_SHIFT = 4,
+ RK3399_GMAC_CLK_SEL_MASK = (3 << RK3399_GMAC_CLK_SEL_SHIFT),
+ RK3399_GMAC_CLK_SEL_125M = (0 << RK3399_GMAC_CLK_SEL_SHIFT),
+ RK3399_GMAC_CLK_SEL_25M = (3 << RK3399_GMAC_CLK_SEL_SHIFT),
+ RK3399_GMAC_CLK_SEL_2_5M = (2 << RK3399_GMAC_CLK_SEL_SHIFT),
+};
+
+/* GRF_SOC_CON6 */
+enum {
+ RK3399_RXCLK_DLY_ENA_GMAC_SHIFT = 15,
+ RK3399_RXCLK_DLY_ENA_GMAC_MASK =
+ (1 << RK3399_RXCLK_DLY_ENA_GMAC_SHIFT),
+ RK3399_RXCLK_DLY_ENA_GMAC_DISABLE = 0,
+ RK3399_RXCLK_DLY_ENA_GMAC_ENABLE =
+ (1 << RK3399_RXCLK_DLY_ENA_GMAC_SHIFT),
+
+ RK3399_TXCLK_DLY_ENA_GMAC_SHIFT = 7,
+ RK3399_TXCLK_DLY_ENA_GMAC_MASK =
+ (1 << RK3399_TXCLK_DLY_ENA_GMAC_SHIFT),
+ RK3399_TXCLK_DLY_ENA_GMAC_DISABLE = 0,
+ RK3399_TXCLK_DLY_ENA_GMAC_ENABLE =
+ (1 << RK3399_TXCLK_DLY_ENA_GMAC_SHIFT),
+
+ RK3399_CLK_RX_DL_CFG_GMAC_SHIFT = 8,
+ RK3399_CLK_RX_DL_CFG_GMAC_MASK =
+ (0x7f << RK3399_CLK_RX_DL_CFG_GMAC_SHIFT),
+
+ RK3399_CLK_TX_DL_CFG_GMAC_SHIFT = 0,
+ RK3399_CLK_TX_DL_CFG_GMAC_MASK =
+ (0x7f << RK3399_CLK_TX_DL_CFG_GMAC_SHIFT),
+};
+
#endif /* __SOC_ROCKCHIP_RK3399_GRF_H__ */