+/* SPDX-License-Identifier: GPL-2.0+ */
/*
* (C) Copyright 2016 Rockchip Electronics Co., Ltd
- *
- * SPDX-License-Identifier: GPL-2.0+
*/
#ifndef __ASM_ARCH_CRU_RK3399_H_
#include <common.h>
+/* Private data for the clock driver - used by rockchip_get_cru() */
+struct rk3399_clk_priv {
+ struct rk3399_cru *cru;
+};
+
+struct rk3399_pmuclk_priv {
+ struct rk3399_pmucru *pmucru;
+};
+
struct rk3399_pmucru {
u32 ppll_con[6];
u32 reserved[0x1a];
#define MHz 1000000
#define KHz 1000
#define OSC_HZ (24*MHz)
-#define APLL_HZ (600*MHz)
+#define LPLL_HZ (600*MHz)
+#define BPLL_HZ (600*MHz)
#define GPLL_HZ (594*MHz)
#define CPLL_HZ (384*MHz)
-#define PPLL_HZ (594*MHz)
+#define PPLL_HZ (676*MHz)
-#define PMU_PCLK_HZ (99*MHz)
+#define PMU_PCLK_HZ (48*MHz)
-#define ACLKM_CORE_HZ (300*MHz)
-#define ATCLK_CORE_HZ (300*MHz)
-#define PCLK_DBG_HZ (100*MHz)
+#define ACLKM_CORE_L_HZ (300*MHz)
+#define ATCLK_CORE_L_HZ (300*MHz)
+#define PCLK_DBG_L_HZ (100*MHz)
+
+#define ACLKM_CORE_B_HZ (300*MHz)
+#define ATCLK_CORE_B_HZ (300*MHz)
+#define PCLK_DBG_B_HZ (100*MHz)
#define PERIHP_ACLK_HZ (148500*KHz)
#define PERIHP_HCLK_HZ (148500*KHz)
APLL_L_600_MHZ,
};
+enum apll_b_frequencies {
+ APLL_B_600_MHZ,
+};
+
+void rk3399_configure_cpu_l(struct rk3399_cru *cru,
+ enum apll_l_frequencies apll_l_freq);
+void rk3399_configure_cpu_b(struct rk3399_cru *cru,
+ enum apll_b_frequencies apll_b_freq);
+
#endif /* __ASM_ARCH_CRU_RK3399_H_ */