+/* SPDX-License-Identifier: GPL-2.0 */
/*
* (C) Copyright 2015 Google, Inc
- *
- * SPDX-License-Identifier: GPL-2.0
*/
#ifndef _ASM_ARCH_CLOCK_H
ROCKCHIP_SYSCON_SGRF,
ROCKCHIP_SYSCON_PMU,
ROCKCHIP_SYSCON_PMUGRF,
+ ROCKCHIP_SYSCON_PMUSGRF,
+ ROCKCHIP_SYSCON_CIC,
+ ROCKCHIP_SYSCON_MSCH,
};
/* Standard Rockchip clock numbers */
return clk_id - 1;
}
+struct sysreset_reg {
+ unsigned int glb_srst_fst_value;
+ unsigned int glb_srst_snd_value;
+};
+
+struct softreset_reg {
+ void __iomem *base;
+ unsigned int sf_reset_offset;
+ unsigned int sf_reset_num;
+};
+
/**
* clk_get_divisor() - Calculate the required clock divisior
*
*/
void *rockchip_get_cru(void);
+/**
+ * rockchip_get_pmucru() - get a pointer to the clock/reset unit registers
+ *
+ * @return pointer to registers, or -ve error on error
+ */
+void *rockchip_get_pmucru(void);
+
struct rk3288_cru;
struct rk3288_grf;
int rockchip_get_clk(struct udevice **devp);
+/*
+ * rockchip_reset_bind() - Bind soft reset device as child of clock device
+ *
+ * @pdev: clock udevice
+ * @reg_offset: the first offset in cru for softreset registers
+ * @reg_number: the reg numbers of softreset registers
+ * @return 0 success, or error value
+ */
+int rockchip_reset_bind(struct udevice *pdev, u32 reg_offset, u32 reg_number);
+
#endif