+/* SPDX-License-Identifier: GPL-2.0 */
/*
* (C) Copyright 2015 Google, Inc
- *
- * SPDX-License-Identifier: GPL-2.0
*/
#ifndef _ASM_ARCH_CLOCK_H
unsigned int glb_srst_snd_value;
};
+struct softreset_reg {
+ void __iomem *base;
+ unsigned int sf_reset_offset;
+ unsigned int sf_reset_num;
+};
+
/**
* clk_get_divisor() - Calculate the required clock divisior
*
int rockchip_get_clk(struct udevice **devp);
+/*
+ * rockchip_reset_bind() - Bind soft reset device as child of clock device
+ *
+ * @pdev: clock udevice
+ * @reg_offset: the first offset in cru for softreset registers
+ * @reg_number: the reg numbers of softreset registers
+ * @return 0 success, or error value
+ */
+int rockchip_reset_bind(struct udevice *pdev, u32 reg_offset, u32 reg_number);
+
#endif