#define OMAP44XX_L4_WKUP_BASE 0x4A300000
#define OMAP44XX_L4_PER_BASE 0x48000000
+#define OMAP44XX_DRAM_ADDR_SPACE_START 0x80000000
+#define OMAP44XX_DRAM_ADDR_SPACE_END 0xD0000000
+
+
/* CONTROL */
#define CTRL_BASE (OMAP44XX_L4_CORE_BASE + 0x2000)
+#define CONTROL_PADCONF_CORE (OMAP44XX_L4_CORE_BASE + 0x100000)
+#define CONTROL_PADCONF_WKUP (OMAP44XX_L4_CORE_BASE + 0x31E000)
/* UART */
#define UART1_BASE (OMAP44XX_L4_PER_BASE + 0x6a000)
#define SYNC_32KTIMER_BASE (OMAP44XX_L4_WKUP_BASE + 0x4000)
/* GPMC */
-#define GPMC_BASE 0x50000000
-
+#define OMAP44XX_GPMC_BASE 0x50000000
+
+/* DMM */
+#define OMAP44XX_DMM_BASE 0x4E000000
+#define DMM_LISA_MAP_BASE (OMAP44XX_DMM_BASE + 0x40)
+#define DMM_LISA_MAP_SYS_SIZE_MASK (7 << 20)
+#define DMM_LISA_MAP_SYS_SIZE_SHIFT 20
+#define DMM_LISA_MAP_SYS_ADDR_MASK (0xFF << 24)
/*
* Hardware Register Details
*/
#define PRM_DEVICE_BASE (PRM_BASE + 0x1B00)
#define PRM_RSTCTRL PRM_DEVICE_BASE
+#define PRM_RSTCTRL_RESET 0x01
#ifndef __ASSEMBLY__