#ifndef _OMAP3_H_
#define _OMAP3_H_
+#include <linux/sizes.h>
+
/* Stuff on L3 Interconnect */
#define SMX_APE_BASE 0x68000000
unsigned int s32k_cr; /* 0x10 */
};
+#define DEVICE_TYPE_SHIFT 0x8
+#define DEVICE_TYPE_MASK (0x7 << DEVICE_TYPE_SHIFT)
+
#endif /* __ASSEMBLY__ */
#ifndef __ASSEMBLY__
#define NON_SECURE_SRAM_START 0x40208000 /* Works for GP & EMU */
#define NON_SECURE_SRAM_END 0x40210000
-#define SRAM_SCRATCH_SPACE_ADDR 0x4020E000
+#define NON_SECURE_SRAM_IMG_END 0x4020F000
+#define SRAM_SCRATCH_SPACE_ADDR (NON_SECURE_SRAM_IMG_END - SZ_1K)
#define LOW_LEVEL_SRAM_STACK 0x4020FFFC
#define AM3517 0x1c00
#define OMAP3730 0x0c00
+#define OMAP3725 0x4c00
+#define AM3715 0x1c00
+#define AM3703 0x5c00
+
+#define OMAP3730_1GHZ 0x0e00
+#define OMAP3725_1GHZ 0x4e00
+#define AM3715_1GHZ 0x1e00
+#define AM3703_1GHZ 0x5e00
/*
* ROM code API related flags
*/
#define OMAP3_GP_ROMCODE_API_L2_INVAL 1
+#define OMAP3_GP_ROMCODE_API_WRITE_L2ACR 2
#define OMAP3_GP_ROMCODE_API_WRITE_ACR 3
/*
/* ABB tranxdone mask */
#define OMAP_ABB_MPU_TXDONE_MASK (0x1 << 26)
+#define OMAP_REBOOT_REASON_OFFSET 0x04
+
/* Boot parameters */
#ifndef __ASSEMBLY__
struct omap_boot_parameters {