global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace

[platform/kernel/u-boot.git] / arch / arm / include / asm / arch-mx6 / imx-regs.h

diff --git a/arch/arm/include/asm/arch-mx6/imx-regs.h b/arch/arm/include/asm/arch-mx6/imx-regs.h
index 48ce0ed..72944af 100644 (file)
--- a/arch/arm/include/asm/arch-mx6/imx-regs.h
+++ b/arch/arm/include/asm/arch-mx6/imx-regs.h
@@ -1,7 +1,6 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
 /*
  * Copyright (C) 2011 Freescale Semiconductor, Inc. All Rights Reserved.
- *
- * SPDX-License-Identifier:    GPL-2.0+
  */
 
 #ifndef __ASM_ARCH_MX6_IMX_REGS_H__
@@ -232,16 +231,19 @@
 #define AIPS2_OFF_BASE_ADDR         (ATZ2_BASE_ADDR + 0x80000)
 #define AIPS3_ON_BASE_ADDR          (ATZ3_BASE_ADDR + 0x7C000)
 #define AIPS3_OFF_BASE_ADDR         (ATZ3_BASE_ADDR + 0x80000)
+#if defined(CONFIG_MX6UL)
+#define CAAM_BASE_ADDR              (ATZ2_BASE_ADDR + 0x40000)
+#else
 #define CAAM_BASE_ADDR              (ATZ2_BASE_ADDR)
+#endif
 #define ARM_BASE_ADDR              (ATZ2_BASE_ADDR + 0x40000)
 
-#define CONFIG_SYS_FSL_SEC_OFFSET   0
-#define CONFIG_SYS_FSL_SEC_ADDR     (CAAM_BASE_ADDR + \
-                                    CONFIG_SYS_FSL_SEC_OFFSET)
-#define CONFIG_SYS_FSL_JR0_OFFSET   0x1000
-#define CONFIG_SYS_FSL_JR0_ADDR     (CAAM_BASE_ADDR + \
-                                    CONFIG_SYS_FSL_JR0_OFFSET)
-#define CONFIG_SYS_FSL_MAX_NUM_OF_SEC  1
+#define CFG_SYS_FSL_SEC_OFFSET   0
+#define CFG_SYS_FSL_SEC_ADDR     (CAAM_BASE_ADDR + \
+                                    CFG_SYS_FSL_SEC_OFFSET)
+#define CFG_SYS_FSL_JR0_OFFSET   0x1000
+#define CFG_SYS_FSL_JR0_ADDR     (CAAM_BASE_ADDR + \
+                                    CFG_SYS_FSL_JR0_OFFSET)
 
 #define USB_PL301_BASE_ADDR         (AIPS2_OFF_BASE_ADDR + 0x0000)
 #define USB_BASE_ADDR               (AIPS2_OFF_BASE_ADDR + 0x4000)
@@ -369,6 +371,7 @@
 #include <asm/mach-imx/regs-lcdif.h>
 #if !(defined(__KERNEL_STRICT_NAMES) || defined(__ASSEMBLY__))
 #include <asm/types.h>
+#include <linux/bitops.h>
 
 /* only for i.MX6SX/UL */
 #define WDOG3_BASE_ADDR (((is_mx6ul() || is_mx6ull()) ?        \
@@ -482,10 +485,11 @@ struct src {
 
 #define src_base ((struct src *)SRC_BASE_ADDR)
 
-#define SRC_SCR_M4_ENABLE_OFFSET                22
-#define SRC_SCR_M4_ENABLE_MASK                  (1 << 22)
-#define SRC_SCR_M4C_NON_SCLR_RST_OFFSET         4
-#define SRC_SCR_M4C_NON_SCLR_RST_MASK           (1 << 4)
+#define SRC_M4_REG_OFFSET              0
+#define SRC_M4_ENABLE_OFFSET           22
+#define SRC_M4_ENABLE_MASK             BIT(22)
+#define SRC_M4C_NON_SCLR_RST_OFFSET    4
+#define SRC_M4C_NON_SCLR_RST_MASK      BIT(4)
 
 /* GPR1 bitfields */
 #define IOMUXC_GPR1_APP_CLK_REQ_N              BIT(30)
@@ -663,46 +667,10 @@ struct gpc {
 #define IOMUXC_GPR2_LVDS_CH0_MODE_ENABLED_DI0          (IOMUXC_GPR2_MODE_ENABLED_DI0<<IOMUXC_GPR2_LVDS_CH0_MODE_OFFSET)
 #define IOMUXC_GPR2_LVDS_CH0_MODE_ENABLED_DI1          (IOMUXC_GPR2_MODE_ENABLED_DI1<<IOMUXC_GPR2_LVDS_CH0_MODE_OFFSET)
 
-/* ECSPI registers */
-struct cspi_regs {
-       u32 rxdata;
-       u32 txdata;
-       u32 ctrl;
-       u32 cfg;
-       u32 intr;
-       u32 dma;
-       u32 stat;
-       u32 period;
-};
-
 /*
  * CSPI register definitions
  */
-#define MXC_ECSPI
-#define MXC_CSPICTRL_EN                (1 << 0)
-#define MXC_CSPICTRL_MODE      (1 << 1)
-#define MXC_CSPICTRL_XCH       (1 << 2)
-#define MXC_CSPICTRL_MODE_MASK (0xf << 4)
-#define MXC_CSPICTRL_CHIPSELECT(x)     (((x) & 0x3) << 12)
-#define MXC_CSPICTRL_BITCOUNT(x)       (((x) & 0xfff) << 20)
-#define MXC_CSPICTRL_PREDIV(x) (((x) & 0xF) << 12)
-#define MXC_CSPICTRL_POSTDIV(x)        (((x) & 0xF) << 8)
-#define MXC_CSPICTRL_SELCHAN(x)        (((x) & 0x3) << 18)
-#define MXC_CSPICTRL_MAXBITS   0xfff
-#define MXC_CSPICTRL_TC                (1 << 7)
-#define MXC_CSPICTRL_RXOVF     (1 << 6)
-#define MXC_CSPIPERIOD_32KHZ   (1 << 15)
-#define MAX_SPI_BYTES  32
 #define SPI_MAX_NUM    4
-
-/* Bit position inside CTRL register to be associated with SS */
-#define MXC_CSPICTRL_CHAN      18
-
-/* Bit position inside CON register to be associated with SS */
-#define MXC_CSPICON_PHA                0  /* SCLK phase control */
-#define MXC_CSPICON_POL                4  /* SCLK polarity */
-#define MXC_CSPICON_SSPOL      12 /* SS polarity */
-#define MXC_CSPICON_CTL                20 /* inactive state of SCLK */
 #if defined(CONFIG_MX6SLL) || defined(CONFIG_MX6SL) || \
        defined(CONFIG_MX6DL) || defined(CONFIG_MX6UL) || defined(CONFIG_MX6ULL)
 #define MXC_SPI_BASE_ADDRESSES \
@@ -992,5 +960,12 @@ struct pwm_regs {
        u32     pr;
        u32     cnr;
 };
-#endif /* __ASSEMBLER__*/
+
+/*
+ * If ROM fail back to USB recover mode, USBPH0_PWD will be clear to use USB
+ * If boot from the other mode, USB0_PWD will keep reset value
+ */
+#define        is_boot_from_usb(void) (!(readl(USB_PHY0_BASE_ADDR) & (1<<20)))
+
+#endif /* __ASSEMBLY__ */
 #endif /* __ASM_ARCH_MX6_IMX_REGS_H__ */