#define ARCH_MXC
-#ifdef CONFIG_MX6UL
-#define CONFIG_SYS_CACHELINE_SIZE 64
-#else
-#define CONFIG_SYS_CACHELINE_SIZE 32
-#endif
-
#define ROMCP_ARB_BASE_ADDR 0x00000000
#define ROMCP_ARB_END_ADDR 0x000FFFFF
/* Defines for Blocks connected via AIPS (SkyBlue) */
#define ATZ1_BASE_ADDR AIPS1_ARB_BASE_ADDR
#define ATZ2_BASE_ADDR AIPS2_ARB_BASE_ADDR
+#define ATZ3_BASE_ADDR AIPS3_ARB_BASE_ADDR
#define AIPS1_BASE_ADDR AIPS1_ON_BASE_ADDR
#define AIPS2_BASE_ADDR AIPS2_ON_BASE_ADDR
+#define AIPS3_BASE_ADDR AIPS3_ON_BASE_ADDR
#define SPDIF_BASE_ADDR (ATZ1_BASE_ADDR + 0x04000)
#define ECSPI1_BASE_ADDR (ATZ1_BASE_ADDR + 0x08000)
#endif
#define UART1_BASE (ATZ1_BASE_ADDR + 0x20000)
#define ESAI1_BASE_ADDR (ATZ1_BASE_ADDR + 0x24000)
+#define UART8_BASE (ATZ1_BASE_ADDR + 0x24000)
#define SSI1_BASE_ADDR (ATZ1_BASE_ADDR + 0x28000)
#define SSI2_BASE_ADDR (ATZ1_BASE_ADDR + 0x2C000)
#define SSI3_BASE_ADDR (ATZ1_BASE_ADDR + 0x30000)
#define AIPS2_ON_BASE_ADDR (ATZ2_BASE_ADDR + 0x7C000)
#define AIPS2_OFF_BASE_ADDR (ATZ2_BASE_ADDR + 0x80000)
+#define AIPS3_ON_BASE_ADDR (ATZ3_BASE_ADDR + 0x7C000)
+#define AIPS3_OFF_BASE_ADDR (ATZ3_BASE_ADDR + 0x80000)
#define CAAM_BASE_ADDR (ATZ2_BASE_ADDR)
#define ARM_BASE_ADDR (ATZ2_BASE_ADDR + 0x40000)
-#define CONFIG_SYS_FSL_SEC_ADDR CAAM_BASE_ADDR
-#define CONFIG_SYS_FSL_JR0_ADDR (CAAM_BASE_ADDR + 0x1000)
+#define CONFIG_SYS_FSL_SEC_OFFSET 0
+#define CONFIG_SYS_FSL_SEC_ADDR (CAAM_BASE_ADDR + \
+ CONFIG_SYS_FSL_SEC_OFFSET)
+#define CONFIG_SYS_FSL_JR0_OFFSET 0x1000
+#define CONFIG_SYS_FSL_JR0_ADDR (CAAM_BASE_ADDR + \
+ CONFIG_SYS_FSL_JR0_OFFSET)
+#define CONFIG_SYS_FSL_MAX_NUM_OF_SEC 1
#define USB_PL301_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x0000)
#define USB_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x4000)
#define CSU_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x40000)
#define IP2APB_PERFMON1_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x44000)
#define IP2APB_PERFMON2_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x48000)
+#define MX6UL_LCDIF1_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x48000)
#ifdef CONFIG_MX6SX
#define DEBUG_MONITOR_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x4C000)
#else
#define IP2APB_TZASC1_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x50000)
#ifdef CONFIG_MX6UL
#define QSPI0_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x60000)
+#define UART6_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x7C000)
#elif defined(CONFIG_MX6SX)
#define SAI1_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x54000)
#define AUDMUX_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x58000)
#define CSI1_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x14000)
#define PXP_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x18000)
#define CSI2_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x1C000)
-#define LCDIF1_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x20000)
-#define LCDIF2_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x24000)
#define VADC_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x28000)
#define VDEC_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x2C000)
#define SPBA_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x3C000)
#define PWM7_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0xAC000)
#define PWM8_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0xB0000)
#endif
+/* Only for i.MX6SX */
+#define LCDIF2_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x24000)
+#define MX6SX_LCDIF1_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x20000)
#define MX6SX_WDOG3_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x88000)
-/* only for i.MX6SX/UL */
-#define WDOG3_BASE_ADDR (is_cpu_type(MXC_CPU_MX6UL) ? \
- MX6UL_WDOG3_BASE_ADDR : MX6SX_WDOG3_BASE_ADDR)
-
-#define CHIP_REV_1_0 0x10
-#define CHIP_REV_1_2 0x12
-#define CHIP_REV_1_5 0x15
-#define CHIP_REV_2_0 0x20
#if !(defined(CONFIG_MX6SX) || defined(CONFIG_MX6UL))
#define IRAM_SIZE 0x00040000
#else
#endif
#define FEC_QUIRK_ENET_MAC
+#include <asm/imx-common/regs-lcdif.h>
#if !(defined(__KERNEL_STRICT_NAMES) || defined(__ASSEMBLY__))
#include <asm/types.h>
+/* only for i.MX6SX/UL */
+#define WDOG3_BASE_ADDR ((is_cpu_type(MXC_CPU_MX6UL) ? \
+ MX6UL_WDOG3_BASE_ADDR : MX6SX_WDOG3_BASE_ADDR))
+#define LCDIF1_BASE_ADDR ((is_cpu_type(MXC_CPU_MX6UL)) ? \
+ MX6UL_LCDIF1_BASE_ADDR : MX6SX_LCDIF1_BASE_ADDR)
+
+
extern void imx_get_mac_from_fuse(int dev_id, unsigned char *mac);
#define SRC_SCR_CORE_1_RESET_OFFSET 14
#define SRC_SCR_CORE_3_ENABLE_OFFSET 24
#define SRC_SCR_CORE_3_ENABLE_MASK (1<<SRC_SCR_CORE_3_ENABLE_OFFSET)
+struct rdc_regs {
+ u32 vir; /* Version information */
+ u32 reserved1[8];
+ u32 stat; /* Status */
+ u32 intctrl; /* Interrupt and Control */
+ u32 intstat; /* Interrupt Status */
+ u32 reserved2[116];
+ u32 mda[32]; /* Master Domain Assignment */
+ u32 reserved3[96];
+ u32 pdap[104]; /* Peripheral Domain Access Permissions */
+ u32 reserved4[88];
+ struct {
+ u32 mrsa; /* Memory Region Start Address */
+ u32 mrea; /* Memory Region End Address */
+ u32 mrc; /* Memory Region Control */
+ u32 mrvs; /* Memory Region Violation Status */
+ } mem_region[55];
+};
+
+struct rdc_sema_regs {
+ u8 gate[64]; /* Gate */
+ u16 rstgt; /* Reset Gate */
+};
+
/* WEIM registers */
struct weim {
u32 cs0gcr1;
u32 gpr10;
};
+#define SRC_SCR_M4_ENABLE_OFFSET 22
+#define SRC_SCR_M4_ENABLE_MASK (1 << 22)
+#define SRC_SCR_M4C_NON_SCLR_RST_OFFSET 4
+#define SRC_SCR_M4C_NON_SCLR_RST_MASK (1 << 4)
+
/* GPR1 bitfields */
+#define IOMUXC_GPR1_APP_CLK_REQ_N BIT(30)
+#define IOMUXC_GPR1_PCIE_EXIT_L1 BIT(28)
+#define IOMUXC_GPR1_PCIE_RDY_L23 BIT(27)
+#define IOMUXC_GPR1_PCIE_ENTER_L1 BIT(26)
+#define IOMUXC_GPR1_MIPI_COLOR_SW BIT(25)
+#define IOMUXC_GPR1_DPI_OFF BIT(24)
+#define IOMUXC_GPR1_EXC_MON_SLVE BIT(22)
#define IOMUXC_GPR1_ENET_CLK_SEL_OFFSET 21
#define IOMUXC_GPR1_ENET_CLK_SEL_MASK (1 << IOMUXC_GPR1_ENET_CLK_SEL_OFFSET)
+#define IOMUXC_GPR1_MIPI_IPU2_MUX_IOMUX BIT(20)
+#define IOMUXC_GPR1_MIPI_IPU1_MUX_IOMUX BIT(19)
+#define IOMUXC_GPR1_PCIE_TEST_PD BIT(18)
+#define IOMUXC_GPR1_IPU_VPU_MUX_IPU2 BIT(17)
+#define IOMUXC_GPR1_PCIE_REF_CLK_EN BIT(16)
+#define IOMUXC_GPR1_USB_EXP_MODE BIT(15)
+#define IOMUXC_GPR1_PCIE_INT BIT(14)
#define IOMUXC_GPR1_USB_OTG_ID_OFFSET 13
#define IOMUXC_GPR1_USB_OTG_ID_SEL_MASK (1 << IOMUXC_GPR1_USB_OTG_ID_OFFSET)
+#define IOMUXC_GPR1_GINT BIT(12)
+#define IOMUXC_GPR1_ADDRS3_MASK (0x3 << 10)
+#define IOMUXC_GPR1_ADDRS3_32MB (0x0 << 10)
+#define IOMUXC_GPR1_ADDRS3_64MB (0x1 << 10)
+#define IOMUXC_GPR1_ADDRS3_128MB (0x2 << 10)
+#define IOMUXC_GPR1_ACT_CS3 BIT(9)
+#define IOMUXC_GPR1_ADDRS2_MASK (0x3 << 7)
+#define IOMUXC_GPR1_ACT_CS2 BIT(6)
+#define IOMUXC_GPR1_ADDRS1_MASK (0x3 << 4)
+#define IOMUXC_GPR1_ACT_CS1 BIT(3)
+#define IOMUXC_GPR1_ADDRS0_OFFSET (1)
+#define IOMUXC_GPR1_ADDRS0_MASK (0x3 << 1)
+#define IOMUXC_GPR1_ACT_CS0 BIT(0)
/* GPR3 bitfields */
#define IOMUXC_GPR3_GPU_DBG_OFFSET 29
#define IOMUXC_GPR3_HDMI_MUX_CTL_OFFSET 2
#define IOMUXC_GPR3_HDMI_MUX_CTL_MASK (3<<IOMUXC_GPR3_HDMI_MUX_CTL_OFFSET)
+/* gpr12 bitfields */
+#define IOMUXC_GPR12_ARMP_IPG_CLK_EN BIT(27)
+#define IOMUXC_GPR12_ARMP_AHB_CLK_EN BIT(26)
+#define IOMUXC_GPR12_ARMP_ATB_CLK_EN BIT(25)
+#define IOMUXC_GPR12_ARMP_APB_CLK_EN BIT(24)
+#define IOMUXC_GPR12_DEVICE_TYPE (0xf << 12)
+#define IOMUXC_GPR12_PCIE_CTL_2 BIT(10)
+#define IOMUXC_GPR12_LOS_LEVEL (0x1f << 4)
struct iomuxc {
#if (defined(CONFIG_MX6SX) || defined(CONFIG_MX6UL))
u32 rsvd7[3];
};
-#if (defined(CONFIG_MX6SX) || defined(CONFIG_MX6UL))
struct fuse_bank4_regs {
u32 sjc_resp_low;
u32 rsvd0[3];
u32 sjc_resp_high;
u32 rsvd1[3];
- u32 mac_addr_low;
+ u32 mac_addr0;
u32 rsvd2[3];
- u32 mac_addr_high;
+ u32 mac_addr1;
u32 rsvd3[3];
- u32 mac_addr2;
+ u32 mac_addr2; /*For i.MX6SX and i.MX6UL*/
u32 rsvd4[7];
u32 gp1;
u32 rsvd5[3];
u32 gp2;
u32 rsvd6[3];
};
-#else
-struct fuse_bank4_regs {
- u32 sjc_resp_low;
- u32 rsvd0[3];
- u32 sjc_resp_high;
- u32 rsvd1[3];
- u32 mac_addr_low;
- u32 rsvd2[3];
- u32 mac_addr_high;
- u32 rsvd3[0xb];
- u32 gp1;
- u32 rsvd4[3];
- u32 gp2;
- u32 rsvd5[3];
-};
-#endif
struct aipstz_regs {
u32 mprot0;
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