Merge git://git.denx.de/u-boot-fdt

[platform/kernel/u-boot.git] / arch / arm / include / asm / arch-mx6 / imx-regs.h

diff --git a/arch/arm/include/asm/arch-mx6/imx-regs.h b/arch/arm/include/asm/arch-mx6/imx-regs.h
index 782d9c4..5314298 100644 (file)
--- a/arch/arm/include/asm/arch-mx6/imx-regs.h
+++ b/arch/arm/include/asm/arch-mx6/imx-regs.h
@@ -215,13 +215,8 @@
 #define AIPS2_OFF_BASE_ADDR         (ATZ2_BASE_ADDR + 0x80000)
 #define CAAM_BASE_ADDR              (ATZ2_BASE_ADDR)
 #define ARM_BASE_ADDR              (ATZ2_BASE_ADDR + 0x40000)
-#ifdef CONFIG_MX6SL
-#define USBO2H_PL301_IPS_BASE_ADDR  (AIPS2_OFF_BASE_ADDR + 0x0000)
-#define USBO2H_USB_BASE_ADDR        (AIPS2_OFF_BASE_ADDR + 0x4000)
-#else
-#define USBOH3_PL301_BASE_ADDR      (AIPS2_OFF_BASE_ADDR + 0x0000)
-#define USBOH3_USB_BASE_ADDR        (AIPS2_OFF_BASE_ADDR + 0x4000)
-#endif
+#define USB_PL301_BASE_ADDR         (AIPS2_OFF_BASE_ADDR + 0x0000)
+#define USB_BASE_ADDR               (AIPS2_OFF_BASE_ADDR + 0x4000)
 
 #define ENET_BASE_ADDR              (AIPS2_OFF_BASE_ADDR + 0x8000)
 #ifdef CONFIG_MX6SL
@@ -324,6 +319,56 @@
 
 extern void imx_get_mac_from_fuse(int dev_id, unsigned char *mac);
 
+#define SRC_SCR_CORE_1_RESET_OFFSET     14
+#define SRC_SCR_CORE_1_RESET_MASK       (1<<SRC_SCR_CORE_1_RESET_OFFSET)
+#define SRC_SCR_CORE_2_RESET_OFFSET     15
+#define SRC_SCR_CORE_2_RESET_MASK       (1<<SRC_SCR_CORE_2_RESET_OFFSET)
+#define SRC_SCR_CORE_3_RESET_OFFSET     16
+#define SRC_SCR_CORE_3_RESET_MASK       (1<<SRC_SCR_CORE_3_RESET_OFFSET)
+#define SRC_SCR_CORE_1_ENABLE_OFFSET    22
+#define SRC_SCR_CORE_1_ENABLE_MASK      (1<<SRC_SCR_CORE_1_ENABLE_OFFSET)
+#define SRC_SCR_CORE_2_ENABLE_OFFSET    23
+#define SRC_SCR_CORE_2_ENABLE_MASK      (1<<SRC_SCR_CORE_2_ENABLE_OFFSET)
+#define SRC_SCR_CORE_3_ENABLE_OFFSET    24
+#define SRC_SCR_CORE_3_ENABLE_MASK      (1<<SRC_SCR_CORE_3_ENABLE_OFFSET)
+
+/* WEIM registers */
+struct weim {
+       u32 cs0gcr1;
+       u32 cs0gcr2;
+       u32 cs0rcr1;
+       u32 cs0rcr2;
+       u32 cs0wcr1;
+       u32 cs0wcr2;
+
+       u32 cs1gcr1;
+       u32 cs1gcr2;
+       u32 cs1rcr1;
+       u32 cs1rcr2;
+       u32 cs1wcr1;
+       u32 cs1wcr2;
+
+       u32 cs2gcr1;
+       u32 cs2gcr2;
+       u32 cs2rcr1;
+       u32 cs2rcr2;
+       u32 cs2wcr1;
+       u32 cs2wcr2;
+
+       u32 cs3gcr1;
+       u32 cs3gcr2;
+       u32 cs3rcr1;
+       u32 cs3rcr2;
+       u32 cs3wcr1;
+       u32 cs3wcr2;
+
+       u32 unused[12];
+
+       u32 wcr;
+       u32 wiar;
+       u32 ear;
+};
+
 /* System Reset Controller (SRC) */
 struct src {
        u32     scr;
@@ -348,6 +393,8 @@ struct src {
 /* GPR1 bitfields */
 #define IOMUXC_GPR1_ENET_CLK_SEL_OFFSET                21
 #define IOMUXC_GPR1_ENET_CLK_SEL_MASK          (1 << IOMUXC_GPR1_ENET_CLK_SEL_OFFSET)
+#define IOMUXC_GPR1_USB_OTG_ID_OFFSET          13
+#define IOMUXC_GPR1_USB_OTG_ID_SEL_MASK                (1 << IOMUXC_GPR1_USB_OTG_ID_OFFSET)
 
 /* GPR3 bitfields */
 #define IOMUXC_GPR3_GPU_DBG_OFFSET             29
@@ -398,9 +445,23 @@ struct src {
 
 
 struct iomuxc {
+#ifdef CONFIG_MX6SX
+       u8 reserved[0x4000];
+#endif
        u32 gpr[14];
-       u32 omux[5];
-       /* mux and pad registers */
+};
+
+struct gpc {
+       u32     cntr;
+       u32     pgr;
+       u32     imr1;
+       u32     imr2;
+       u32     imr3;
+       u32     imr4;
+       u32     isr1;
+       u32     isr2;
+       u32     isr3;
+       u32     isr4;
 };
 
 #define IOMUXC_GPR2_COUNTER_RESET_VAL_OFFSET           20
@@ -500,6 +561,7 @@ struct cspi_regs {
 #define MXC_CSPICTRL_RXOVF     (1 << 6)
 #define MXC_CSPIPERIOD_32KHZ   (1 << 15)
 #define MAX_SPI_BYTES  32
+#define SPI_MAX_NUM    4
 
 /* Bit position inside CTRL register to be associated with SS */
 #define MXC_CSPICTRL_CHAN      18
@@ -772,5 +834,21 @@ struct wdog_regs {
        u16     wmcr;   /* Miscellaneous Control */
 };
 
+#define PWMCR_PRESCALER(x)     (((x - 1) & 0xFFF) << 4)
+#define PWMCR_DOZEEN           (1 << 24)
+#define PWMCR_WAITEN           (1 << 23)
+#define PWMCR_DBGEN            (1 << 22)
+#define PWMCR_CLKSRC_IPG_HIGH  (2 << 16)
+#define PWMCR_CLKSRC_IPG       (1 << 16)
+#define PWMCR_EN               (1 << 0)
+
+struct pwm_regs {
+       u32     cr;
+       u32     sr;
+       u32     ir;
+       u32     sar;
+       u32     pr;
+       u32     cnr;
+};
 #endif /* __ASSEMBLER__*/
 #endif /* __ASM_ARCH_MX6_IMX_REGS_H__ */