Merge git://git.denx.de/u-boot-fdt

[platform/kernel/u-boot.git] / arch / arm / include / asm / arch-mx6 / imx-regs.h

diff --git a/arch/arm/include/asm/arch-mx6/imx-regs.h b/arch/arm/include/asm/arch-mx6/imx-regs.h
index 2631beb..5314298 100644 (file)
--- a/arch/arm/include/asm/arch-mx6/imx-regs.h
+++ b/arch/arm/include/asm/arch-mx6/imx-regs.h
@@ -215,13 +215,8 @@
 #define AIPS2_OFF_BASE_ADDR         (ATZ2_BASE_ADDR + 0x80000)
 #define CAAM_BASE_ADDR              (ATZ2_BASE_ADDR)
 #define ARM_BASE_ADDR              (ATZ2_BASE_ADDR + 0x40000)
-#ifdef CONFIG_MX6SL
-#define USBO2H_PL301_IPS_BASE_ADDR  (AIPS2_OFF_BASE_ADDR + 0x0000)
-#define USBO2H_USB_BASE_ADDR        (AIPS2_OFF_BASE_ADDR + 0x4000)
-#else
-#define USBOH3_PL301_BASE_ADDR      (AIPS2_OFF_BASE_ADDR + 0x0000)
-#define USBOH3_USB_BASE_ADDR        (AIPS2_OFF_BASE_ADDR + 0x4000)
-#endif
+#define USB_PL301_BASE_ADDR         (AIPS2_OFF_BASE_ADDR + 0x0000)
+#define USB_BASE_ADDR               (AIPS2_OFF_BASE_ADDR + 0x4000)
 
 #define ENET_BASE_ADDR              (AIPS2_OFF_BASE_ADDR + 0x8000)
 #ifdef CONFIG_MX6SL
@@ -337,6 +332,43 @@ extern void imx_get_mac_from_fuse(int dev_id, unsigned char *mac);
 #define SRC_SCR_CORE_3_ENABLE_OFFSET    24
 #define SRC_SCR_CORE_3_ENABLE_MASK      (1<<SRC_SCR_CORE_3_ENABLE_OFFSET)
 
+/* WEIM registers */
+struct weim {
+       u32 cs0gcr1;
+       u32 cs0gcr2;
+       u32 cs0rcr1;
+       u32 cs0rcr2;
+       u32 cs0wcr1;
+       u32 cs0wcr2;
+
+       u32 cs1gcr1;
+       u32 cs1gcr2;
+       u32 cs1rcr1;
+       u32 cs1rcr2;
+       u32 cs1wcr1;
+       u32 cs1wcr2;
+
+       u32 cs2gcr1;
+       u32 cs2gcr2;
+       u32 cs2rcr1;
+       u32 cs2rcr2;
+       u32 cs2wcr1;
+       u32 cs2wcr2;
+
+       u32 cs3gcr1;
+       u32 cs3gcr2;
+       u32 cs3rcr1;
+       u32 cs3rcr2;
+       u32 cs3wcr1;
+       u32 cs3wcr2;
+
+       u32 unused[12];
+
+       u32 wcr;
+       u32 wiar;
+       u32 ear;
+};
+
 /* System Reset Controller (SRC) */
 struct src {
        u32     scr;
@@ -419,6 +451,19 @@ struct iomuxc {
        u32 gpr[14];
 };
 
+struct gpc {
+       u32     cntr;
+       u32     pgr;
+       u32     imr1;
+       u32     imr2;
+       u32     imr3;
+       u32     imr4;
+       u32     isr1;
+       u32     isr2;
+       u32     isr3;
+       u32     isr4;
+};
+
 #define IOMUXC_GPR2_COUNTER_RESET_VAL_OFFSET           20
 #define IOMUXC_GPR2_COUNTER_RESET_VAL_MASK             (3<<IOMUXC_GPR2_COUNTER_RESET_VAL_OFFSET)
 #define IOMUXC_GPR2_LVDS_CLK_SHIFT_OFFSET              16