Merge branch 'master' of git://git.denx.de/u-boot-socfpga
[platform/kernel/u-boot.git] / arch / arm / include / asm / arch-mx6 / crm_regs.h
index 85e301c..39f3c07 100644 (file)
@@ -228,6 +228,8 @@ struct mxc_ccm_reg {
 #ifdef CONFIG_MX6SX
 #define MXC_CCM_CSCMR1_QSPI1_CLK_SEL_MASK              (0x7 << 7)
 #define MXC_CCM_CSCMR1_QSPI1_CLK_SEL_OFFSET            7
+#endif
+#if (defined(CONFIG_MX6SL) || defined(CONFIG_MX6SX))
 #define MXC_CCM_CSCMR1_PER_CLK_SEL_MASK                        (1 << 6)
 #define MXC_CCM_CSCMR1_PER_CLK_SEL_OFFSET              6
 #endif
@@ -931,10 +933,10 @@ struct mxc_ccm_reg {
 #define BF_ANADIG_PLL_VIDEO_RSVD0(v)  \
        (((v) << 22) & BM_ANADIG_PLL_VIDEO_RSVD0)
 #define BM_ANADIG_PLL_VIDEO_SSC_EN 0x00200000
-#define BP_ANADIG_PLL_VIDEO_TEST_DIV_SELECT      19
-#define BM_ANADIG_PLL_VIDEO_TEST_DIV_SELECT 0x00180000
-#define BF_ANADIG_PLL_VIDEO_TEST_DIV_SELECT(v)  \
-       (((v) << 19) & BM_ANADIG_PLL_VIDEO_TEST_DIV_SELECT)
+#define BP_ANADIG_PLL_VIDEO_POST_DIV_SELECT      19
+#define BM_ANADIG_PLL_VIDEO_POST_DIV_SELECT 0x00180000
+#define BF_ANADIG_PLL_VIDEO_POST_DIV_SELECT(v)  \
+       (((v) << 19) & BM_ANADIG_PLL_VIDEO_POST_DIV_SELECT)
 #define BM_ANADIG_PLL_VIDEO_PFD_OFFSET_EN 0x00040000
 #define BM_ANADIG_PLL_VIDEO_DITHER_ENABLE 0x00020000
 #define BM_ANADIG_PLL_VIDEO_BYPASS 0x00010000