/*
* (C) Copyright 2009 Freescale Semiconductor, Inc.
*
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
+ * SPDX-License-Identifier: GPL-2.0+
*/
#ifndef __ASM_ARCH_MX5_IMX_REGS_H__
*/
#define WBED 1
-#define CS0_128 0
-#define CS0_64M_CS1_64M 1
-#define CS0_64M_CS1_32M_CS2_32M 2
-#define CS0_32M_CS1_32M_CS2_32M_CS3_32M 3
-
/*
* CSPI register definitions
*/
#define MXC_CSPICTRL_CHAN 18
/* Bit position inside CON register to be associated with SS */
-#define MXC_CSPICON_POL 4
-#define MXC_CSPICON_PHA 0
-#define MXC_CSPICON_SSPOL 12
+#define MXC_CSPICON_PHA 0 /* SCLK phase control */
+#define MXC_CSPICON_POL 4 /* SCLK polarity */
+#define MXC_CSPICON_SSPOL 12 /* SS polarity */
+#define MXC_CSPICON_CTL 20 /* inactive state of SCLK */
#define MXC_SPI_BASE_ADDRESSES \
CSPI1_BASE_ADDR, \
CSPI2_BASE_ADDR, \
#define DP_MFD_216 (4 - 1)
#define DP_MFN_216 3
-#define CHIP_REV_1_0 0x10
-#define CHIP_REV_1_1 0x11
-#define CHIP_REV_2_0 0x20
-#define CHIP_REV_2_5 0x25
-#define CHIP_REV_3_0 0x30
-
-#define BOARD_REV_1_0 0x0
-#define BOARD_REV_2_0 0x1
-
-#define BOARD_VER_OFFSET 0x8
-
#define IMX_IIM_BASE (IIM_BASE_ADDR)
#if !(defined(__KERNEL_STRICT_NAMES) || defined(__ASSEMBLY__))
#if defined(CONFIG_MX51)
struct iomuxc {
- u32 gpr0;
- u32 gpr1;
+ u32 gpr[2];
u32 omux0;
u32 omux1;
u32 omux2;
};
#elif defined(CONFIG_MX53)
struct iomuxc {
- u32 gpr0;
- u32 gpr1;
- u32 gpr2;
+ u32 gpr[3];
u32 omux0;
u32 omux1;
u32 omux2;
u32 sdat;
u32 prev;
u32 srev;
- u32 preg_p;
+ u32 prg_p;
u32 scs0;
u32 scs1;
u32 scs2;
struct fuse_bank {
u32 fuse_regs[0x20];
u32 fuse_rsvd[0xe0];
+#if defined(CONFIG_MX51)
} bank[4];
+#elif defined(CONFIG_MX53)
+ } bank[5];
+#endif
};
struct fuse_bank0_regs {
- u32 fuse0_23[24];
+ u32 fuse0_7[8];
+ u32 uid[8];
+ u32 fuse16_23[8];
+#if defined(CONFIG_MX51)
+ u32 imei[8];
+#elif defined(CONFIG_MX53)
u32 gp[8];
+#endif
};
struct fuse_bank1_regs {
u32 fuse15_31[0x11];
};
+#if defined(CONFIG_MX53)
+struct fuse_bank4_regs {
+ u32 fuse0_4[5];
+ u32 gp[3];
+ u32 fuse8_31[0x18];
+};
+#endif
+
#endif /* __ASSEMBLER__*/
#endif /* __ASM_ARCH_MX5_IMX_REGS_H__ */