keystone2: enable OSR clock domain for K2L SoC

[platform/kernel/u-boot.git] / arch / arm / include / asm / arch-keystone / hardware-k2l.h

diff --git a/arch/arm/include/asm/arch-keystone/hardware-k2l.h b/arch/arm/include/asm/arch-keystone/hardware-k2l.h
index c1fa3af..05532ad 100644 (file)
--- a/arch/arm/include/asm/arch-keystone/hardware-k2l.h
+++ b/arch/arm/include/asm/arch-keystone/hardware-k2l.h
@@ -60,6 +60,30 @@
 #define KS2_CIC2_DDR3_ECC_IRQ_NUM      0x0D3
 #define KS2_CIC2_DDR3_ECC_CHAN_NUM     0x01D
 
+/* OSR */
+#define KS2_OSR_DATA_BASE              0x70000000      /* OSR data base */
+#define KS2_OSR_CFG_BASE               0x02348c00      /* OSR config base */
+#define KS2_OSR_ECC_VEC                        0x08            /* ECC Vector reg */
+#define KS2_OSR_ECC_CTRL               0x14            /* ECC control reg */
+
+/* OSR ECC Vector register */
+#define KS2_OSR_ECC_VEC_TRIG_RD                BIT(15)         /* trigger a read op */
+#define KS2_OSR_ECC_VEC_RD_DONE                BIT(24)         /* read complete */
+
+#define KS2_OSR_ECC_VEC_RAM_ID_SH      0               /* RAM ID shift */
+#define KS2_OSR_ECC_VEC_RD_ADDR_SH     16              /* read address shift */
+
+/* OSR ECC control register */
+#define KS2_OSR_ECC_CTRL_EN            BIT(0)          /* ECC enable bit */
+#define KS2_OSR_ECC_CTRL_CHK           BIT(1)          /* ECC check bit */
+#define KS2_OSR_ECC_CTRL_RMW           BIT(2)          /* ECC check bit */
+
+/* Number of OSR RAM banks */
+#define KS2_OSR_NUM_RAM_BANKS          4
+
+/* OSR memory size */
+#define KS2_OSR_SIZE                   0x100000
+
 /* Number of DSP cores */
 #define KS2_NUM_DSPS                   4