#define IOMUXC_GPR_BASE_ADDR 0x30340000
#define OCOTP_BASE_ADDR 0x30350000
#define ANATOP_BASE_ADDR 0x30360000
+#define SNVS_BASE_ADDR 0x30370000
#define CCM_BASE_ADDR 0x30380000
#define SRC_BASE_ADDR 0x30390000
#define GPC_BASE_ADDR 0x303A0000
#define UART4_BASE_ADDR 0x30A60000
#define USDHC1_BASE_ADDR 0x30B40000
#define USDHC2_BASE_ADDR 0x30B50000
+#define QSPI0_AMBA_BASE 0x08000000
#ifdef CONFIG_IMX8MM
#define USDHC3_BASE_ADDR 0x30B60000
#endif
+#define UART_BASE_ADDR(n) ( \
+ !!sizeof(struct { \
+ static_assert((n) >= 1 && (n) <= 4); \
+ int pad; \
+ }) * ( \
+ (n) == 1 ? UART1_BASE_ADDR : \
+ (n) == 2 ? UART2_BASE_ADDR : \
+ (n) == 3 ? UART3_BASE_ADDR : \
+ UART4_BASE_ADDR) \
+ )
#define TZASC_BASE_ADDR 0x32F80000
#define SRC_DDRC_RCR_ADDR 0x30391000
#define SRC_DDRC2_RCR_ADDR 0x30391004
+#define APBH_DMA_ARB_BASE_ADDR 0x33000000
+#define APBH_DMA_ARB_END_ADDR 0x33007FFF
+#define MXS_APBH_BASE APBH_DMA_ARB_BASE_ADDR
+
+#define MXS_GPMI_BASE (APBH_DMA_ARB_BASE_ADDR + 0x02000)
+#define MXS_BCH_BASE (APBH_DMA_ARB_BASE_ADDR + 0x04000)
+
#define DDRC_DDR_SS_GPR0 0x3d000000
#define DDRC_IPS_BASE_ADDR(X) (0x3d400000 + ((X) * 0x2000000))
#define DDR_CSD1_BASE_ADDR 0x40000000
+#define IOMUXC_GPR_GPR1_GPR_ENET_QOS_INTF_SEL_MASK 0x70000
+#define FEC_QUIRK_ENET_MAC
+
+#define CAAM_ARB_BASE_ADDR (0x00100000)
+#define CAAM_ARB_END_ADDR (0x00107FFF)
+#define CAAM_IPS_BASE_ADDR (0x30900000)
+#define CFG_SYS_FSL_SEC_OFFSET (0)
+#define CFG_SYS_FSL_SEC_ADDR (CAAM_IPS_BASE_ADDR + \
+ CFG_SYS_FSL_SEC_OFFSET)
+#define CFG_SYS_FSL_JR0_OFFSET (0x1000)
+#define CFG_SYS_FSL_JR0_ADDR (CFG_SYS_FSL_SEC_ADDR + \
+ CFG_SYS_FSL_JR0_OFFSET)
#if !defined(__ASSEMBLY__)
#include <asm/types.h>
#include <linux/bitops.h>
#include <stdbool.h>
-#define GPR_TZASC_EN BIT(0)
-#define GPR_TZASC_EN_LOCK BIT(16)
+#define GPR_TZASC_EN BIT(0)
+#define GPR_TZASC_ID_SWAP_BYPASS BIT(1)
+#define GPR_TZASC_EN_LOCK BIT(16)
+#define GPR_TZASC_ID_SWAP_BYPASS_LOCK BIT(17)
#define SRC_SCR_M4_ENABLE_OFFSET 3
#define SRC_SCR_M4_ENABLE_MASK BIT(3)
#define SRC_DDR1_RCR_CORE_RESET_N_MASK BIT(1)
#define SRC_DDR1_RCR_PRESET_N_MASK BIT(0)
+#define SNVS_LPSR 0x4c
+#define SNVS_LPLVDR 0x64
+#define SNVS_LPPGDR_INIT 0x41736166
+
struct iomuxc_gpr_base_regs {
u32 gpr[47];
};
} bank[0];
};
+#ifdef CONFIG_IMX8MP
+struct fuse_bank0_regs {
+ u32 lock;
+ u32 rsvd0[7];
+ u32 uid_low;
+ u32 rsvd1[3];
+ u32 uid_high;
+ u32 rsvd2[3];
+};
+#else
struct fuse_bank0_regs {
u32 lock;
u32 rsvd0[3];
u32 uid_high;
u32 rsvd2[7];
};
+#endif
struct fuse_bank1_regs {
u32 tester3;
u32 ddr2_rcr;
};
+#define PWMCR_PRESCALER(x) (((x - 1) & 0xFFF) << 4)
+#define PWMCR_DOZEEN (1 << 24)
+#define PWMCR_WAITEN (1 << 23)
+#define PWMCR_DBGEN (1 << 22)
+#define PWMCR_CLKSRC_IPG_HIGH (2 << 16)
+#define PWMCR_CLKSRC_IPG (1 << 16)
+#define PWMCR_EN (1 << 0)
+
+struct pwm_regs {
+ u32 cr;
+ u32 sr;
+ u32 ir;
+ u32 sar;
+ u32 pr;
+ u32 cnr;
+};
+
#define WDOG_WDT_MASK BIT(3)
#define WDOG_WDZST_MASK BIT(0)
struct wdog_regs {