global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace

[platform/kernel/u-boot.git] / arch / arm / include / asm / arch-imx8m / imx-regs.h

diff --git a/arch/arm/include/asm/arch-imx8m/imx-regs.h b/arch/arm/include/asm/arch-imx8m/imx-regs.h
index b800da1..586847f 100644 (file)
--- a/arch/arm/include/asm/arch-imx8m/imx-regs.h
+++ b/arch/arm/include/asm/arch-imx8m/imx-regs.h
@@ -27,6 +27,7 @@
 #define IOMUXC_GPR_BASE_ADDR   0x30340000
 #define OCOTP_BASE_ADDR                0x30350000
 #define ANATOP_BASE_ADDR       0x30360000
+#define SNVS_BASE_ADDR         0x30370000
 #define CCM_BASE_ADDR          0x30380000
 #define SRC_BASE_ADDR          0x30390000
 #define GPC_BASE_ADDR          0x303A0000
@@ -45,9 +46,20 @@
 #define UART4_BASE_ADDR                0x30A60000
 #define USDHC1_BASE_ADDR       0x30B40000
 #define USDHC2_BASE_ADDR       0x30B50000
+#define QSPI0_AMBA_BASE     0x08000000
 #ifdef CONFIG_IMX8MM
 #define USDHC3_BASE_ADDR       0x30B60000
 #endif
+#define UART_BASE_ADDR(n)      (                       \
+       !!sizeof(struct {                               \
+               static_assert((n) >= 1 && (n) <= 4);    \
+               int pad;                                \
+               }) * (                                  \
+       (n) == 1 ? UART1_BASE_ADDR :                    \
+       (n) == 2 ? UART2_BASE_ADDR :                    \
+       (n) == 3 ? UART3_BASE_ADDR :                    \
+       UART4_BASE_ADDR)                                \
+       )
 
 #define TZASC_BASE_ADDR                0x32F80000
 
@@ -58,6 +70,13 @@
 #define SRC_DDRC_RCR_ADDR      0x30391000
 #define SRC_DDRC2_RCR_ADDR     0x30391004
 
+#define APBH_DMA_ARB_BASE_ADDR 0x33000000
+#define APBH_DMA_ARB_END_ADDR  0x33007FFF
+#define MXS_APBH_BASE          APBH_DMA_ARB_BASE_ADDR
+
+#define MXS_GPMI_BASE          (APBH_DMA_ARB_BASE_ADDR + 0x02000)
+#define MXS_BCH_BASE           (APBH_DMA_ARB_BASE_ADDR + 0x04000)
+
 #define DDRC_DDR_SS_GPR0       0x3d000000
 #define DDRC_IPS_BASE_ADDR(X)  (0x3d400000 + ((X) * 0x2000000))
 #define DDR_CSD1_BASE_ADDR     0x40000000
@@ -68,20 +87,21 @@
 #define CAAM_ARB_BASE_ADDR              (0x00100000)
 #define CAAM_ARB_END_ADDR               (0x00107FFF)
 #define CAAM_IPS_BASE_ADDR              (0x30900000)
-#define CONFIG_SYS_FSL_SEC_OFFSET       (0)
-#define CONFIG_SYS_FSL_SEC_ADDR         (CAAM_IPS_BASE_ADDR + \
-                                        CONFIG_SYS_FSL_SEC_OFFSET)
-#define CONFIG_SYS_FSL_JR0_OFFSET       (0x1000)
-#define CONFIG_SYS_FSL_JR0_ADDR         (CONFIG_SYS_FSL_SEC_ADDR + \
-                                        CONFIG_SYS_FSL_JR0_OFFSET)
-#define CONFIG_SYS_FSL_MAX_NUM_OF_SEC   1
+#define CFG_SYS_FSL_SEC_OFFSET       (0)
+#define CFG_SYS_FSL_SEC_ADDR         (CAAM_IPS_BASE_ADDR + \
+                                        CFG_SYS_FSL_SEC_OFFSET)
+#define CFG_SYS_FSL_JR0_OFFSET       (0x1000)
+#define CFG_SYS_FSL_JR0_ADDR         (CFG_SYS_FSL_SEC_ADDR + \
+                                        CFG_SYS_FSL_JR0_OFFSET)
 #if !defined(__ASSEMBLY__)
 #include <asm/types.h>
 #include <linux/bitops.h>
 #include <stdbool.h>
 
-#define GPR_TZASC_EN           BIT(0)
-#define GPR_TZASC_EN_LOCK      BIT(16)
+#define GPR_TZASC_EN                                   BIT(0)
+#define GPR_TZASC_ID_SWAP_BYPASS               BIT(1)
+#define GPR_TZASC_EN_LOCK                              BIT(16)
+#define GPR_TZASC_ID_SWAP_BYPASS_LOCK  BIT(17)
 
 #define SRC_SCR_M4_ENABLE_OFFSET       3
 #define SRC_SCR_M4_ENABLE_MASK         BIT(3)
@@ -94,6 +114,10 @@
 #define SRC_DDR1_RCR_CORE_RESET_N_MASK BIT(1)
 #define SRC_DDR1_RCR_PRESET_N_MASK     BIT(0)
 
+#define SNVS_LPSR                      0x4c
+#define SNVS_LPLVDR                    0x64
+#define SNVS_LPPGDR_INIT               0x41736166
+
 struct iomuxc_gpr_base_regs {
        u32 gpr[47];
 };
@@ -326,6 +350,23 @@ struct src {
        u32 ddr2_rcr;
 };
 
+#define PWMCR_PRESCALER(x)     (((x - 1) & 0xFFF) << 4)
+#define PWMCR_DOZEEN           (1 << 24)
+#define PWMCR_WAITEN           (1 << 23)
+#define PWMCR_DBGEN            (1 << 22)
+#define PWMCR_CLKSRC_IPG_HIGH  (2 << 16)
+#define PWMCR_CLKSRC_IPG       (1 << 16)
+#define PWMCR_EN               (1 << 0)
+
+struct pwm_regs {
+       u32     cr;
+       u32     sr;
+       u32     ir;
+       u32     sar;
+       u32     pr;
+       u32     cnr;
+};
+
 #define WDOG_WDT_MASK  BIT(3)
 #define WDOG_WDZST_MASK        BIT(0)
 struct wdog_regs {