/* SPDX-License-Identifier: GPL-2.0+ */
/*
- * Copyright 2018 NXP
+ * Copyright 2018, 2021 NXP
*/
#ifndef __ASM_ARCH_IMX8_REGS_H__
#define __ASM_ARCH_IMX8_REGS_H__
+#define ARCH_MXC
+
#define LPUART_BASE 0x5A060000
#define GPT1_BASE_ADDR 0x5D140000
#define LPI2C4_BASE_ADDR 0x5A830000
#define LPI2C5_BASE_ADDR 0x5A840000
+#define FEC_QUIRK_ENET_MAC
+
#ifdef CONFIG_IMX8QXP
#define LVDS0_PHYCTRL_BASE 0x56221000
#define LVDS1_PHYCTRL_BASE 0x56241000
#define USB_BASE_ADDR 0x5b0d0000
#define USB_PHY0_BASE_ADDR 0x5b100000
+#define CFG_SYS_FSL_SEC_ADDR (0x31400000)
+
#endif /* __ASM_ARCH_IMX8_REGS_H__ */