armv8: fsl-layerscape: identify boot source from PORSR register

[platform/kernel/u-boot.git] / arch / arm / include / asm / arch-fsl-layerscape / soc.h

diff --git a/arch/arm/include/asm/arch-fsl-layerscape/soc.h b/arch/arm/include/asm/arch-fsl-layerscape/soc.h
index cb760b5..d327c7b 100644 (file)
--- a/arch/arm/include/asm/arch-fsl-layerscape/soc.h
+++ b/arch/arm/include/asm/arch-fsl-layerscape/soc.h
@@ -1,8 +1,7 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
 /*
  * Copyright 2017 NXP
  * Copyright 2015 Freescale Semiconductor
- *
- * SPDX-License-Identifier:    GPL-2.0+
  */
 
 #ifndef _ASM_ARMV8_FSL_LAYERSCAPE_SOC_H_
@@ -54,6 +53,23 @@ struct cpu_type {
 
 #define CPU_TYPE_ENTRY(n, v, nc) \
        { .name = #n, .soc_ver = SVR_##v, .num_cores = (nc)}
+
+#ifdef CONFIG_TFABOOT
+enum boot_src {
+       BOOT_SOURCE_RESERVED = 0,
+       BOOT_SOURCE_IFC_NOR,
+       BOOT_SOURCE_IFC_NAND,
+       BOOT_SOURCE_QSPI_NOR,
+       BOOT_SOURCE_QSPI_NAND,
+       BOOT_SOURCE_XSPI_NOR,
+       BOOT_SOURCE_XSPI_NAND,
+       BOOT_SOURCE_SD_MMC,
+       BOOT_SOURCE_SD_MMC2,
+       BOOT_SOURCE_I2C1_EXTENDED,
+};
+
+enum boot_src get_boot_src(void);
+#endif
 #endif
 #define SVR_WO_E               0xFFFFFE
 #define SVR_LS1012A            0x870400
@@ -86,39 +102,7 @@ struct cpu_type {
 #define SVR_DEV(svr)           ((svr) >> 8)
 #define IS_SVR_DEV(svr, dev)   (((svr) >> 16) == (dev))
 
-/* ahci port register default value */
-#define AHCI_PORT_PHY_1_CFG    0xa003fffe
-#define AHCI_PORT_PHY2_CFG     0x28184d1f
-#define AHCI_PORT_PHY3_CFG     0x0e081509
-#define AHCI_PORT_TRANS_CFG    0x08000029
-#define AHCI_PORT_AXICC_CFG    0x3fffffff
-
 #ifndef __ASSEMBLY__
-/* AHCI (sata) register map */
-struct ccsr_ahci {
-       u32 res1[0xa4/4];       /* 0x0 - 0xa4 */
-       u32 pcfg;       /* port config */
-       u32 ppcfg;      /* port phy1 config */
-       u32 pp2c;       /* port phy2 config */
-       u32 pp3c;       /* port phy3 config */
-       u32 pp4c;       /* port phy4 config */
-       u32 pp5c;       /* port phy5 config */
-       u32 axicc;      /* AXI cache control */
-       u32 paxic;      /* port AXI config */
-       u32 axipc;      /* AXI PROT control */
-       u32 ptc;        /* port Trans Config */
-       u32 pts;        /* port Trans Status */
-       u32 plc;        /* port link config */
-       u32 plc1;       /* port link config1 */
-       u32 plc2;       /* port link config2 */
-       u32 pls;        /* port link status */
-       u32 pls1;       /* port link status1 */
-       u32 pcmdc;      /* port CMD config */
-       u32 ppcs;       /* port phy control status */
-       u32 pberr;      /* port 0/1 BIST error */
-       u32 cmds;       /* port 0/1 CMD status error */
-};
-
 #ifdef CONFIG_FSL_LSCH3
 void fsl_lsch3_early_init_f(void);
 int get_core_volt_from_fuse(void);
@@ -127,6 +111,12 @@ void fsl_lsch2_early_init_f(void);
 int setup_chip_volt(void);
 /* Setup core vdd in unit mV */
 int board_setup_core_volt(u32 vdd);
+#ifdef CONFIG_FSL_PFE
+void init_pfe_scfg_dcfg_regs(void);
+#endif
+#endif
+#ifdef CONFIG_QSPI_AHB_INIT
+int qspi_ahb_init(void);
 #endif
 
 void cpu_name(char *name);