pci/layerscape: add support for LS1043A PCIe LUT register access

[platform/kernel/u-boot.git] / arch / arm / include / asm / arch-fsl-layerscape / soc.h

diff --git a/arch/arm/include/asm/arch-fsl-layerscape/soc.h b/arch/arm/include/asm/arch-fsl-layerscape/soc.h
index f131f57..8691906 100644 (file)
--- a/arch/arm/include/asm/arch-fsl-layerscape/soc.h
+++ b/arch/arm/include/asm/arch-fsl-layerscape/soc.h
@@ -23,6 +23,14 @@
 #define scfg_out32(a, v)   out_be32(a, v)
 #endif
 
+#ifdef CONFIG_SYS_FSL_PEX_LUT_LE
+#define pex_lut_in32(a)       in_le32(a)
+#define pex_lut_out32(a, v)   out_le32(a, v)
+#elif defined(CONFIG_SYS_FSL_PEX_LUT_BE)
+#define pex_lut_in32(a)       in_be32(a)
+#define pex_lut_out32(a, v)   out_be32(a, v)
+#endif
+
 struct cpu_type {
        char name[15];
        u32 soc_ver;
@@ -33,6 +41,7 @@ struct cpu_type {
        { .name = #n, .soc_ver = SVR_##v, .num_cores = (nc)}
 
 #define SVR_WO_E               0xFFFFFE
+#define SVR_LS1043             0x879204
 #define SVR_LS2045             0x870120
 #define SVR_LS2080             0x870110
 #define SVR_LS2085             0x870100
@@ -42,6 +51,11 @@ struct cpu_type {
 #define SVR_SOC_VER(svr)       (((svr) >> 8) & SVR_WO_E)
 #define IS_E_PROCESSOR(svr)    (!((svr >> 8) & 0x1))
 
+#ifdef CONFIG_FSL_LSCH3
 void fsl_lsch3_early_init_f(void);
+#elif defined(CONFIG_FSL_LSCH2)
+void fsl_lsch2_early_init_f(void);
+#endif
+
 void cpu_name(char *name);
 #endif /* _ASM_ARMV8_FSL_LAYERSCAPE_SOC_H_ */