/*
+ * Copyright 2017 NXP
* Copyright 2015 Freescale Semiconductor
*
* SPDX-License-Identifier: GPL-2.0+
#ifndef _ASM_ARMV8_FSL_LAYERSCAPE_SOC_H_
#define _ASM_ARMV8_FSL_LAYERSCAPE_SOC_H_
+#ifndef __ASSEMBLY__
+#include <linux/types.h>
+#ifdef CONFIG_FSL_LSCH2
+#include <asm/arch/immap_lsch2.h>
+#endif
+#ifdef CONFIG_FSL_LSCH3
+#include <asm/arch/immap_lsch3.h>
+#endif
+#endif
+
#ifdef CONFIG_SYS_FSL_CCSR_GUR_LE
#define gur_in32(a) in_le32(a)
#define gur_out32(a, v) out_le32(a, v)
#define SVR_LS2084A 0x870910
#define SVR_LS2048A 0x870920
#define SVR_LS2044A 0x870930
+#define SVR_LS2081A 0x870919
+#define SVR_LS2041A 0x870915
#define SVR_DEV_LS2080A 0x8701
#define SVR_MAJ(svr) (((svr) >> 4) & 0xf)
#define SVR_MIN(svr) (((svr) >> 0) & 0xf)
+#define SVR_REV(svr) (((svr) >> 0) & 0xff)
#define SVR_SOC_VER(svr) (((svr) >> 8) & SVR_WO_E)
#define IS_E_PROCESSOR(svr) (!((svr >> 8) & 0x1))
#define IS_SVR_REV(svr, maj, min) \
void fsl_lsch3_early_init_f(void);
#elif defined(CONFIG_FSL_LSCH2)
void fsl_lsch2_early_init_f(void);
+int setup_chip_volt(void);
+/* Setup core vdd in unit mV */
+int board_setup_core_volt(u32 vdd);
#endif
void cpu_name(char *name);
bool soc_has_dp_ddr(void);
bool soc_has_aiop(void);
#endif
+
#endif /* _ASM_ARMV8_FSL_LAYERSCAPE_SOC_H_ */