Merge branch 'master' of git://git.denx.de/u-boot-samsung

[platform/kernel/u-boot.git] / arch / arm / include / asm / arch-fsl-layerscape / soc.h

diff --git a/arch/arm/include/asm/arch-fsl-layerscape/soc.h b/arch/arm/include/asm/arch-fsl-layerscape/soc.h
index 0729b7f..497afe7 100644 (file)
--- a/arch/arm/include/asm/arch-fsl-layerscape/soc.h
+++ b/arch/arm/include/asm/arch-fsl-layerscape/soc.h
@@ -1,4 +1,5 @@
 /*
+ * Copyright 2017 NXP
  * Copyright 2015 Freescale Semiconductor
  *
  * SPDX-License-Identifier:    GPL-2.0+
@@ -7,6 +8,16 @@
 #ifndef _ASM_ARMV8_FSL_LAYERSCAPE_SOC_H_
 #define _ASM_ARMV8_FSL_LAYERSCAPE_SOC_H_
 
+#ifndef __ASSEMBLY__
+#include <linux/types.h>
+#ifdef CONFIG_FSL_LSCH2
+#include <asm/arch/immap_lsch2.h>
+#endif
+#ifdef CONFIG_FSL_LSCH3
+#include <asm/arch/immap_lsch3.h>
+#endif
+#endif
+
 #ifdef CONFIG_SYS_FSL_CCSR_GUR_LE
 #define gur_in32(a)       in_le32(a)
 #define gur_out32(a, v)   out_le32(a, v)
@@ -30,7 +41,7 @@
 #define pex_lut_in32(a)       in_be32(a)
 #define pex_lut_out32(a, v)   out_be32(a, v)
 #endif
-
+#ifndef __ASSEMBLY__
 struct cpu_type {
        char name[15];
        u32 soc_ver;
@@ -39,7 +50,7 @@ struct cpu_type {
 
 #define CPU_TYPE_ENTRY(n, v, nc) \
        { .name = #n, .soc_ver = SVR_##v, .num_cores = (nc)}
-
+#endif
 #define SVR_WO_E               0xFFFFFE
 #define SVR_LS1012A            0x870400
 #define SVR_LS1043A            0x879200
@@ -50,9 +61,18 @@ struct cpu_type {
 #define SVR_LS2080A            0x870110
 #define SVR_LS2085A            0x870100
 #define SVR_LS2040A            0x870130
+#define SVR_LS2088A            0x870900
+#define SVR_LS2084A            0x870910
+#define SVR_LS2048A            0x870920
+#define SVR_LS2044A            0x870930
+#define SVR_LS2081A            0x870919
+#define SVR_LS2041A            0x870915
+
+#define SVR_DEV_LS2080A                0x8701
 
 #define SVR_MAJ(svr)           (((svr) >> 4) & 0xf)
 #define SVR_MIN(svr)           (((svr) >> 0) & 0xf)
+#define SVR_REV(svr)           (((svr) >> 0) & 0xff)
 #define SVR_SOC_VER(svr)       (((svr) >> 8) & SVR_WO_E)
 #define IS_E_PROCESSOR(svr)    (!((svr >> 8) & 0x1))
 #define IS_SVR_REV(svr, maj, min) \
@@ -61,7 +81,9 @@ struct cpu_type {
 /* ahci port register default value */
 #define AHCI_PORT_PHY_1_CFG    0xa003fffe
 #define AHCI_PORT_TRANS_CFG    0x08000029
+#define AHCI_PORT_AXICC_CFG    0x3fffffff
 
+#ifndef __ASSEMBLY__
 /* AHCI (sata) register map */
 struct ccsr_ahci {
        u32 res1[0xa4/4];       /* 0x0 - 0xa4 */
@@ -91,6 +113,9 @@ struct ccsr_ahci {
 void fsl_lsch3_early_init_f(void);
 #elif defined(CONFIG_FSL_LSCH2)
 void fsl_lsch2_early_init_f(void);
+int setup_chip_volt(void);
+/* Setup core vdd in unit mV */
+int board_setup_core_volt(u32 vdd);
 #endif
 
 void cpu_name(char *name);
@@ -104,4 +129,6 @@ void erratum_a010315(void);
 
 bool soc_has_dp_ddr(void);
 bool soc_has_aiop(void);
+#endif
+
 #endif /* _ASM_ARMV8_FSL_LAYERSCAPE_SOC_H_ */