global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace

[platform/kernel/u-boot.git] / arch / arm / include / asm / arch-fsl-layerscape / immap_lsch3.h

diff --git a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h
index 304cd79..f1ffb23 100644 (file)
--- a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h
+++ b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h
@@ -9,19 +9,19 @@
 #ifndef __ARCH_FSL_LSCH3_IMMAP_H_
 #define __ARCH_FSL_LSCH3_IMMAP_H_
 
-#define CONFIG_SYS_FSL_DDR_ADDR                        (CONFIG_SYS_IMMR + 0x00080000)
-#define CONFIG_SYS_FSL_DDR2_ADDR               (CONFIG_SYS_IMMR + 0x00090000)
-#define CONFIG_SYS_FSL_DDR3_ADDR               0x08210000
-#define CONFIG_SYS_FSL_GUTS_ADDR               (CONFIG_SYS_IMMR + 0x00E00000)
-#define CONFIG_SYS_FSL_PMU_ADDR                        (CONFIG_SYS_IMMR + 0x00E30000)
+#define CFG_SYS_FSL_DDR_ADDR                   (CONFIG_SYS_IMMR + 0x00080000)
+#define CFG_SYS_FSL_DDR2_ADDR          (CONFIG_SYS_IMMR + 0x00090000)
+#define CFG_SYS_FSL_DDR3_ADDR          0x08210000
+#define CFG_SYS_FSL_GUTS_ADDR          (CONFIG_SYS_IMMR + 0x00E00000)
+#define CFG_SYS_FSL_PMU_ADDR                   (CONFIG_SYS_IMMR + 0x00E30000)
 #if defined(CONFIG_ARCH_LX2160A) || defined(CONFIG_ARCH_LX2162A)
-#define CONFIG_SYS_FSL_RST_ADDR                        (CONFIG_SYS_IMMR + 0x00e88180)
+#define CFG_SYS_FSL_RST_ADDR                   (CONFIG_SYS_IMMR + 0x00e88180)
 #else
-#define CONFIG_SYS_FSL_RST_ADDR                        (CONFIG_SYS_IMMR + 0x00E60000)
+#define CFG_SYS_FSL_RST_ADDR                   (CONFIG_SYS_IMMR + 0x00E60000)
 #endif
-#define CONFIG_SYS_FSL_CH3_CLK_GRPA_ADDR       (CONFIG_SYS_IMMR + 0x00300000)
-#define CONFIG_SYS_FSL_CH3_CLK_GRPB_ADDR       (CONFIG_SYS_IMMR + 0x00310000)
-#define CONFIG_SYS_FSL_CH3_CLK_CTRL_ADDR       (CONFIG_SYS_IMMR + 0x00370000)
+#define CFG_SYS_FSL_CH3_CLK_GRPA_ADDR  (CONFIG_SYS_IMMR + 0x00300000)
+#define CFG_SYS_FSL_CH3_CLK_GRPB_ADDR  (CONFIG_SYS_IMMR + 0x00310000)
+#define CFG_SYS_FSL_CH3_CLK_CTRL_ADDR  (CONFIG_SYS_IMMR + 0x00370000)
 #ifndef CONFIG_NXP_LSCH3_2
 #define SYS_FSL_QSPI_ADDR                      (CONFIG_SYS_IMMR + 0x010c0000)
 #else
@@ -29,8 +29,8 @@
 #define SYS_NXP_FSPI_LUTKEY_BASE_ADDR          0x18
 #define SYS_NXP_FSPI_LUT_BASE_ADDR             0x200
 #endif
-#define CONFIG_SYS_FSL_ESDHC_ADDR              (CONFIG_SYS_IMMR + 0x01140000)
-#define FSL_ESDHC1_BASE_ADDR                   CONFIG_SYS_FSL_ESDHC_ADDR
+#define CFG_SYS_FSL_ESDHC_ADDR         (CONFIG_SYS_IMMR + 0x01140000)
+#define FSL_ESDHC1_BASE_ADDR                   CFG_SYS_FSL_ESDHC_ADDR
 #define FSL_ESDHC2_BASE_ADDR                   (CONFIG_SYS_IMMR + 0x01150000)
 #ifndef CONFIG_NXP_LSCH3_2
 #define CONFIG_SYS_IFC_ADDR                    (CONFIG_SYS_IMMR + 0x01240000)
@@ -38,21 +38,20 @@
 #define CONFIG_SYS_NS16550_COM1                        (CONFIG_SYS_IMMR + 0x011C0500)
 #define CONFIG_SYS_NS16550_COM2                        (CONFIG_SYS_IMMR + 0x011C0600)
 #define SYS_FSL_LS2080A_LS2085A_TIMER_ADDR     0x023d0000
-#define CONFIG_SYS_FSL_TIMER_ADDR              0x023e0000
-#define CONFIG_SYS_FSL_PMU_CLTBENR             (CONFIG_SYS_FSL_PMU_ADDR + \
+#define CFG_SYS_FSL_TIMER_ADDR         0x023e0000
+#define CFG_SYS_FSL_PMU_CLTBENR                (CFG_SYS_FSL_PMU_ADDR + \
                                                 0x18A0)
-#define FSL_PMU_PCTBENR_OFFSET (CONFIG_SYS_FSL_PMU_ADDR + 0x8A0)
-#define FSL_LSCH3_SVR          (CONFIG_SYS_FSL_GUTS_ADDR + 0xA4)
+#define FSL_PMU_PCTBENR_OFFSET (CFG_SYS_FSL_PMU_ADDR + 0x8A0)
+#define FSL_LSCH3_SVR          (CFG_SYS_FSL_GUTS_ADDR + 0xA4)
 
-#define CONFIG_SYS_FSL_WRIOP1_ADDR             (CONFIG_SYS_IMMR + 0x7B80000)
-#define CONFIG_SYS_FSL_WRIOP1_MDIO1    (CONFIG_SYS_FSL_WRIOP1_ADDR + 0x16000)
-#define CONFIG_SYS_FSL_WRIOP1_MDIO2    (CONFIG_SYS_FSL_WRIOP1_ADDR + 0x17000)
-#define CONFIG_SYS_FSL_LSCH3_SERDES_ADDR       (CONFIG_SYS_IMMR + 0xEA0000)
+#define CFG_SYS_FSL_WRIOP1_ADDR                (CONFIG_SYS_IMMR + 0x7B80000)
+#define CFG_SYS_FSL_WRIOP1_MDIO1       (CFG_SYS_FSL_WRIOP1_ADDR + 0x16000)
+#define CFG_SYS_FSL_WRIOP1_MDIO2       (CFG_SYS_FSL_WRIOP1_ADDR + 0x17000)
+#define CFG_SYS_FSL_LSCH3_SERDES_ADDR  (CONFIG_SYS_IMMR + 0xEA0000)
 
-#define CONFIG_SYS_FSL_DCSR_DDR_ADDR           0x70012c000ULL
-#define CONFIG_SYS_FSL_DCSR_DDR2_ADDR          0x70012d000ULL
-#define CONFIG_SYS_FSL_DCSR_DDR3_ADDR          0x700132000ULL
-#define CONFIG_SYS_FSL_DCSR_DDR4_ADDR          0x700133000ULL
+#define CFG_SYS_FSL_DCSR_DDR_ADDR              0x70012c000ULL
+#define CFG_SYS_FSL_DCSR_DDR2_ADDR             0x70012d000ULL
+#define CFG_SYS_FSL_DCSR_DDR3_ADDR             0x700132000ULL
 
 #define I2C1_BASE_ADDR                         (CONFIG_SYS_IMMR + 0x01000000)
 #define I2C2_BASE_ADDR                         (CONFIG_SYS_IMMR + 0x01010000)
@@ -109,16 +108,16 @@
 #define CONFIG_SYS_SFP_ADDR            (CONFIG_SYS_IMMR + 0x00e80200)
 
 /* SEC */
-#define CONFIG_SYS_FSL_SEC_OFFSET              0x07000000ull
-#define CONFIG_SYS_FSL_JR0_OFFSET              0x07010000ull
-#define FSL_SEC_JR0_OFFSET                     CONFIG_SYS_FSL_JR0_OFFSET
+#define CFG_SYS_FSL_SEC_OFFSET         0x07000000ull
+#define CFG_SYS_FSL_JR0_OFFSET         0x07010000ull
+#define FSL_SEC_JR0_OFFSET                     CFG_SYS_FSL_JR0_OFFSET
 #define FSL_SEC_JR1_OFFSET                     0x07020000ull
 #define FSL_SEC_JR2_OFFSET                     0x07030000ull
 #define FSL_SEC_JR3_OFFSET                     0x07040000ull
-#define CONFIG_SYS_FSL_SEC_ADDR \
-       (CONFIG_SYS_IMMR + CONFIG_SYS_FSL_SEC_OFFSET)
-#define CONFIG_SYS_FSL_JR0_ADDR \
-       (CONFIG_SYS_IMMR + CONFIG_SYS_FSL_JR0_OFFSET)
+#define CFG_SYS_FSL_SEC_ADDR \
+       (CONFIG_SYS_IMMR + CFG_SYS_FSL_SEC_OFFSET)
+#define CFG_SYS_FSL_JR0_ADDR \
+       (CONFIG_SYS_IMMR + CFG_SYS_FSL_JR0_OFFSET)
 #define FSL_SEC_JR0_BASE_ADDR (CONFIG_SYS_IMMR + FSL_SEC_JR0_OFFSET)
 #define FSL_SEC_JR1_BASE_ADDR (CONFIG_SYS_IMMR + FSL_SEC_JR1_OFFSET)
 #define FSL_SEC_JR2_BASE_ADDR (CONFIG_SYS_IMMR + FSL_SEC_JR2_OFFSET)