Merge tag 'u-boot-atmel-fixes-2021.01-b' of https://gitlab.denx.de/u-boot/custodians...

[platform/kernel/u-boot.git] / arch / arm / include / asm / arch-fsl-layerscape / immap_lsch3.h

diff --git a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h
index 299201b..b61666e 100644 (file)
--- a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h
+++ b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h
@@ -2,7 +2,7 @@
 /*
  * LayerScape Internal Memory Map
  *
- * Copyright 2017-2019 NXP
+ * Copyright 2017-2020 NXP
  * Copyright 2014 Freescale Semiconductor, Inc.
  */
 
@@ -15,7 +15,7 @@
 #define CONFIG_SYS_FSL_DDR3_ADDR               0x08210000
 #define CONFIG_SYS_FSL_GUTS_ADDR               (CONFIG_SYS_IMMR + 0x00E00000)
 #define CONFIG_SYS_FSL_PMU_ADDR                        (CONFIG_SYS_IMMR + 0x00E30000)
-#ifdef CONFIG_ARCH_LX2160A
+#if defined(CONFIG_ARCH_LX2160A) || defined(CONFIG_ARCH_LX2162A)
 #define CONFIG_SYS_FSL_RST_ADDR                        (CONFIG_SYS_IMMR + 0x00e88180)
 #else
 #define CONFIG_SYS_FSL_RST_ADDR                        (CONFIG_SYS_IMMR + 0x00E60000)
@@ -198,12 +198,12 @@
 #define CONFIG_SYS_PCIE2_ADDR                  (CONFIG_SYS_IMMR + 0x2500000)
 #define CONFIG_SYS_PCIE3_ADDR                  (CONFIG_SYS_IMMR + 0x2600000)
 #define CONFIG_SYS_PCIE4_ADDR                  (CONFIG_SYS_IMMR + 0x2700000)
-#ifdef CONFIG_ARCH_LX2160A
+#if defined(CONFIG_ARCH_LX2160A) || defined(CONFIG_ARCH_LX2162A)
 #define SYS_PCIE5_ADDR                         (CONFIG_SYS_IMMR + 0x2800000)
 #define SYS_PCIE6_ADDR                         (CONFIG_SYS_IMMR + 0x2900000)
 #endif
 
-#ifdef CONFIG_ARCH_LX2160A
+#if defined(CONFIG_ARCH_LX2160A) || defined(CONFIG_ARCH_LX2162A)
 #define CONFIG_SYS_PCIE1_PHYS_ADDR             0x8000000000ULL
 #define CONFIG_SYS_PCIE2_PHYS_ADDR             0x8800000000ULL
 #define CONFIG_SYS_PCIE3_PHYS_ADDR             0x9000000000ULL
@@ -232,7 +232,12 @@
 #define DCFG_PORSR1                    0x000
 #define DCFG_PORSR1_RCW_SRC            0xff800000
 #define DCFG_PORSR1_RCW_SRC_NOR                0x12f00000
+#define DCFG_RCWSR12                   0x12c
+#define DCFG_RCWSR12_SDHC_SHIFT                24
+#define DCFG_RCWSR12_SDHC_MASK         0x7
 #define DCFG_RCWSR13                   0x130
+#define DCFG_RCWSR13_SDHC_SHIFT                3
+#define DCFG_RCWSR13_SDHC_MASK         0x7
 #define DCFG_RCWSR13_DSPI              (0 << 8)
 #define DCFG_RCWSR15                   0x138
 #define DCFG_RCWSR15_IFCGRPABASE_QSPI  0x3
@@ -262,7 +267,7 @@
        defined(CONFIG_ARCH_LS1028A)
 #define USB_PHY_RX_EQ_VAL_3            0x0380
 #define USB_PHY_RX_EQ_VAL_4            0x0b80
-#elif defined(CONFIG_ARCH_LX2160A)
+#elif defined(CONFIG_ARCH_LX2160A) || defined(CONFIG_ARCH_LX2162A)
 #define USB_PHY_RX_EQ_VAL_3            0x0080
 #define USB_PHY_RX_EQ_VAL_4            0x0880
 #endif
@@ -386,12 +391,12 @@ struct ccsr_gur {
 #define FSL_CHASSIS3_SRDS2_PRTCL_SHIFT FSL_CHASSIS3_RCWSR28_SRDS2_PRTCL_SHIFT
 #define FSL_CHASSIS3_SRDS1_REGSR       29
 #define FSL_CHASSIS3_SRDS2_REGSR       29
-#elif defined(CONFIG_ARCH_LX2160A)
+#elif defined(CONFIG_ARCH_LX2160A) || defined(CONFIG_ARCH_LX2162A)
 #define FSL_CHASSIS3_EC1_REGSR  27
 #define FSL_CHASSIS3_EC2_REGSR  27
 #define FSL_CHASSIS3_EC1_REGSR_PRTCL_MASK      0x00000003
 #define FSL_CHASSIS3_EC1_REGSR_PRTCL_SHIFT     0
-#define FSL_CHASSIS3_EC2_REGSR_PRTCL_MASK      0x00000007
+#define FSL_CHASSIS3_EC2_REGSR_PRTCL_MASK      0x0000000C
 #define FSL_CHASSIS3_EC2_REGSR_PRTCL_SHIFT     2
 #define FSL_CHASSIS3_RCWSR28_SRDS1_PRTCL_MASK   0x001F0000
 #define FSL_CHASSIS3_RCWSR28_SRDS1_PRTCL_SHIFT  16
@@ -584,5 +589,5 @@ struct ccsr_serdes {
        u8 res5[0x19fc - 0xa00];
 };
 
-#endif /*__ASSEMBLY__*/
+#endif /*__ASSEMBLY__ */
 #endif /* __ARCH_FSL_LSCH3_IMMAP_H_ */