Merge branch 'master' of git://git.denx.de/u-boot-sh

[platform/kernel/u-boot.git] / arch / arm / include / asm / arch-fsl-layerscape / immap_lsch3.h

diff --git a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h
index 0535224..24c1b0e 100644 (file)
--- a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h
+++ b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h
@@ -2,7 +2,7 @@
 /*
  * LayerScape Internal Memory Map
  *
- * Copyright 2017-2018 NXP
+ * Copyright 2017-2019 NXP
  * Copyright 2014 Freescale Semiconductor, Inc.
  */
 
@@ -167,10 +167,25 @@
 #define CONFIG_SYS_PCIE2_ADDR                  (CONFIG_SYS_IMMR + 0x2500000)
 #define CONFIG_SYS_PCIE3_ADDR                  (CONFIG_SYS_IMMR + 0x2600000)
 #define CONFIG_SYS_PCIE4_ADDR                  (CONFIG_SYS_IMMR + 0x2700000)
-#ifdef CONFIG_ARCH_LS1088A
+#ifdef CONFIG_ARCH_LX2160A
+#define SYS_PCIE5_ADDR                         (CONFIG_SYS_IMMR + 0x2800000)
+#define SYS_PCIE6_ADDR                         (CONFIG_SYS_IMMR + 0x2900000)
+#endif
+
+#ifdef CONFIG_ARCH_LX2160A
+#define CONFIG_SYS_PCIE1_PHYS_ADDR             0x8000000000ULL
+#define CONFIG_SYS_PCIE2_PHYS_ADDR             0x8800000000ULL
+#define CONFIG_SYS_PCIE3_PHYS_ADDR             0x9000000000ULL
+#define CONFIG_SYS_PCIE4_PHYS_ADDR             0x9800000000ULL
+#define SYS_PCIE5_PHYS_ADDR                    0xa000000000ULL
+#define SYS_PCIE6_PHYS_ADDR                    0xa800000000ULL
+#elif CONFIG_ARCH_LS1088A
 #define CONFIG_SYS_PCIE1_PHYS_ADDR             0x2000000000ULL
 #define CONFIG_SYS_PCIE2_PHYS_ADDR             0x2800000000ULL
 #define CONFIG_SYS_PCIE3_PHYS_ADDR             0x3000000000ULL
+#elif CONFIG_ARCH_LS1028A
+#define CONFIG_SYS_PCIE1_PHYS_ADDR             0x8000000000ULL
+#define CONFIG_SYS_PCIE2_PHYS_ADDR             0x8800000000ULL
 #else
 #define CONFIG_SYS_PCIE1_PHYS_ADDR             0x1000000000ULL
 #define CONFIG_SYS_PCIE2_PHYS_ADDR             0x1200000000ULL
@@ -350,6 +365,14 @@ struct ccsr_gur {
 #define FSL_CHASSIS3_SRDS1_REGSR       29
 #define FSL_CHASSIS3_SRDS2_REGSR       29
 #define FSL_CHASSIS3_SRDS3_REGSR       29
+#define FSL_CHASSIS3_RCWSR12_REGSR         12
+#define FSL_CHASSIS3_RCWSR13_REGSR         13
+#define FSL_CHASSIS3_SDHC1_BASE_PMUX_MASK  0x07000000
+#define FSL_CHASSIS3_SDHC1_BASE_PMUX_SHIFT 24
+#define FSL_CHASSIS3_SDHC2_BASE_PMUX_MASK  0x00000038
+#define FSL_CHASSIS3_SDHC2_BASE_PMUX_SHIFT 3
+#define FSL_CHASSIS3_IIC5_PMUX_MASK        0x00000E00
+#define FSL_CHASSIS3_IIC5_PMUX_SHIFT       9
 #elif defined(CONFIG_ARCH_LS1088A)
 #define FSL_CHASSIS3_EC1_REGSR  26
 #define FSL_CHASSIS3_EC2_REGSR  26
@@ -367,6 +390,12 @@ struct ccsr_gur {
 #define FSL_CHASSIS3_SRDS2_PRTCL_SHIFT FSL_CHASSIS3_RCWSR30_SRDS2_PRTCL_SHIFT
 #define FSL_CHASSIS3_SRDS1_REGSR       29
 #define FSL_CHASSIS3_SRDS2_REGSR       30
+#elif defined(CONFIG_ARCH_LS1028A)
+#define        FSL_CHASSIS3_RCWSR29_SRDS1_PRTCL_MASK   0xFFFF0000
+#define        FSL_CHASSIS3_RCWSR29_SRDS1_PRTCL_SHIFT  16
+#define FSL_CHASSIS3_SRDS1_PRTCL_MASK  FSL_CHASSIS3_RCWSR29_SRDS1_PRTCL_MASK
+#define FSL_CHASSIS3_SRDS1_PRTCL_SHIFT FSL_CHASSIS3_RCWSR29_SRDS1_PRTCL_SHIFT
+#define FSL_CHASSIS3_SRDS1_REGSR       29
 #endif
 #define RCW_SB_EN_REG_INDEX    9
 #define RCW_SB_EN_MASK         0x00000400