Merge tag 'u-boot-atmel-fixes-2021.01-b' of https://gitlab.denx.de/u-boot/custodians...

[platform/kernel/u-boot.git] / arch / arm / include / asm / arch-fsl-layerscape / cpu.h

diff --git a/arch/arm/include/asm/arch-fsl-layerscape/cpu.h b/arch/arm/include/asm/arch-fsl-layerscape/cpu.h
index d62754e..4335aa0 100644 (file)
--- a/arch/arm/include/asm/arch-fsl-layerscape/cpu.h
+++ b/arch/arm/include/asm/arch-fsl-layerscape/cpu.h
@@ -1,6 +1,6 @@
 /* SPDX-License-Identifier: GPL-2.0+ */
 /*
- * Copyright 2017-2018 NXP
+ * Copyright 2017-2018, 2020 NXP
  * Copyright 2014-2015, Freescale Semiconductor
  */
 
@@ -34,15 +34,26 @@
 #define CONFIG_SYS_FSL_QBMAN_BASE      0x818000000
 #define CONFIG_SYS_FSL_QBMAN_SIZE      0x8000000
 #define CONFIG_SYS_FSL_QBMAN_SIZE_1    0x4000000
+#ifdef CONFIG_ARCH_LS2080A
 #define CONFIG_SYS_PCIE1_PHYS_SIZE     0x200000000
 #define CONFIG_SYS_PCIE2_PHYS_SIZE     0x200000000
 #define CONFIG_SYS_PCIE3_PHYS_SIZE     0x200000000
 #define CONFIG_SYS_PCIE4_PHYS_SIZE     0x200000000
+#else
+#define CONFIG_SYS_PCIE1_PHYS_SIZE     0x800000000
+#define CONFIG_SYS_PCIE2_PHYS_SIZE     0x800000000
+#ifndef CONFIG_SYS_PCIE3_PHYS_SIZE
+#define CONFIG_SYS_PCIE3_PHYS_SIZE     0x800000000
+#endif
+#define CONFIG_SYS_PCIE4_PHYS_SIZE     0x800000000
+#define SYS_PCIE5_PHYS_SIZE            0x800000000
+#define SYS_PCIE6_PHYS_SIZE            0x800000000
+#endif
 #define CONFIG_SYS_FSL_WRIOP1_BASE     0x4300000000
 #define CONFIG_SYS_FSL_WRIOP1_SIZE     0x100000000
 #define CONFIG_SYS_FSL_AIOP1_BASE      0x4b00000000
 #define CONFIG_SYS_FSL_AIOP1_SIZE      0x100000000
-#ifndef CONFIG_ARCH_LX2160A
+#if !defined(CONFIG_ARCH_LX2160A) || !defined(CONFIG_ARCH_LX2162)
 #define CONFIG_SYS_FSL_PEBUF_BASE      0x4c00000000
 #else
 #define CONFIG_SYS_FSL_PEBUF_BASE      0x1c00000000