global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace

[platform/kernel/u-boot.git] / arch / arm / include / asm / arch-fsl-layerscape / config.h

diff --git a/arch/arm/include/asm/arch-fsl-layerscape/config.h b/arch/arm/include/asm/arch-fsl-layerscape/config.h
index 1791b97..ff752c2 100644 (file)
--- a/arch/arm/include/asm/arch-fsl-layerscape/config.h
+++ b/arch/arm/include/asm/arch-fsl-layerscape/config.h
@@ -24,7 +24,7 @@
 #define SPL_TLB_SETBACK        0x1000000       /* 16MB under effective memory top */
 
 #ifdef CONFIG_ARCH_LS2080A
-#define CONFIG_SYS_FSL_CLUSTER_CLOCKS          { 1, 1, 4, 4 }
+#define CFG_SYS_FSL_CLUSTER_CLOCKS             { 1, 1, 4, 4 }
 #define        SRDS_MAX_LANES  8
 #define CONFIG_SYS_PAGE_SIZE           0x10000
 #ifndef L1_CACHE_BYTES
@@ -32,9 +32,9 @@
 #define L1_CACHE_BYTES         BIT(L1_CACHE_SHIFT)
 #endif
 
-#define CONFIG_SYS_FSL_OCRAM_BASE      0x18000000 /* initial RAM */
+#define CFG_SYS_FSL_OCRAM_BASE 0x18000000 /* initial RAM */
 #define SYS_FSL_OCRAM_SPACE_SIZE       0x00200000 /* 2M space */
-#define CONFIG_SYS_FSL_OCRAM_SIZE      0x00020000 /* Real size 128K */
+#define CFG_SYS_FSL_OCRAM_SIZE 0x00020000 /* Real size 128K */
 
 /* DDR */
 #define CONFIG_SYS_DDR_BLOCK1_SIZE     ((phys_size_t)2 << 30)
@@ -94,13 +94,8 @@
 #define EPU_EPCTR5             0x700060a14ULL
 #define EPU_EPGCR              0x700060000ULL
 
-#define CONFIG_SYS_FSL_ERRATUM_A008751
-
-#define CONFIG_SYS_FSL_MAX_NUM_OF_SEC          1
-
 #elif defined(CONFIG_ARCH_LS1088A)
-#define CONFIG_SYS_FSL_NUM_CC_PLLS             3
-#define CONFIG_SYS_FSL_CLUSTER_CLOCKS          { 1, 1 }
+#define CFG_SYS_FSL_CLUSTER_CLOCKS             { 1, 1 }
 #define CONFIG_SYS_PAGE_SIZE           0x10000
 
 #define        SRDS_MAX_LANES  4
@@ -131,10 +126,9 @@
 #define CONFIG_MAX_MEM_MAPPED          CONFIG_SYS_DDR_BLOCK1_SIZE
 
 /* DCFG - GUR */
-#define CONFIG_SYS_FSL_MAX_NUM_OF_SEC  1
-#define CONFIG_SYS_FSL_OCRAM_BASE      0x18000000 /* initial RAM */
+#define CFG_SYS_FSL_OCRAM_BASE 0x18000000 /* initial RAM */
 #define SYS_FSL_OCRAM_SPACE_SIZE       0x00200000 /* 2M space */
-#define CONFIG_SYS_FSL_OCRAM_SIZE      0x00020000 /* Real size 128K */
+#define CFG_SYS_FSL_OCRAM_SIZE 0x00020000 /* Real size 128K */
 
 /* LX2160A/LX2162A Soc Support */
 #elif defined(CONFIG_ARCH_LX2160A) || defined(CONFIG_ARCH_LX2162A)
@@ -145,14 +139,13 @@
 #define L1_CACHE_SHIFT         6
 #define L1_CACHE_BYTES         BIT(L1_CACHE_SHIFT)
 #endif
-#define CONFIG_SYS_FSL_CLUSTER_CLOCKS          { 1, 1, 1, 1, 4, 4, 4, 4 }
-#define CONFIG_SYS_FSL_NUM_CC_PLLS             4
+#define CFG_SYS_FSL_CLUSTER_CLOCKS             { 1, 1, 1, 1, 4, 4, 4, 4 }
 
 #define CONFIG_SYS_PAGE_SIZE                   0x10000
 
-#define CONFIG_SYS_FSL_OCRAM_BASE              0x18000000 /* initial RAM */
+#define CFG_SYS_FSL_OCRAM_BASE         0x18000000 /* initial RAM */
 #define SYS_FSL_OCRAM_SPACE_SIZE               0x00200000 /* 2M space */
-#define CONFIG_SYS_FSL_OCRAM_SIZE              0x00040000 /* Real size 256K */
+#define CFG_SYS_FSL_OCRAM_SIZE         0x00040000 /* Real size 256K */
 
 /* DDR */
 #define CONFIG_SYS_DDR_BLOCK1_SIZE             ((phys_size_t)2 << 30)
@@ -167,11 +160,8 @@
 
 /* DCFG - GUR */
 
-#define CONFIG_SYS_FSL_MAX_NUM_OF_SEC          1
-
 #elif defined(CONFIG_ARCH_LS1028A)
-#define CONFIG_SYS_FSL_NUM_CC_PLLS             3
-#define CONFIG_SYS_FSL_CLUSTER_CLOCKS          { 1, 1 }
+#define CFG_SYS_FSL_CLUSTER_CLOCKS             { 1, 1 }
 #define CONFIG_FSL_TZASC_400
 
 /* TZ Protection Controller Definitions */
@@ -190,9 +180,9 @@
 #define        SRDS_MAX_LANES  4
 #define        SRDS_BITS_PER_LANE      4
 
-#define CONFIG_SYS_FSL_OCRAM_BASE              0x18000000 /* initial RAM */
+#define CFG_SYS_FSL_OCRAM_BASE         0x18000000 /* initial RAM */
 #define SYS_FSL_OCRAM_SPACE_SIZE               0x00200000 /* 2M */
-#define CONFIG_SYS_FSL_OCRAM_SIZE              0x00040000 /* Real size 256K */
+#define CFG_SYS_FSL_OCRAM_SIZE         0x00040000 /* Real size 256K */
 
 /* Generic Interrupt Controller Definitions */
 #define GICD_BASE                              0x06000000
@@ -206,24 +196,19 @@
 #define CONFIG_MAX_MEM_MAPPED          CONFIG_SYS_DDR_BLOCK1_SIZE
 
 /* SEC */
-#define CONFIG_SYS_FSL_MAX_NUM_OF_SEC          1
 
 /* DCFG - GUR */
 
 #elif defined(CONFIG_FSL_LSCH2)
-#define CONFIG_SYS_FSL_OCRAM_BASE              0x10000000 /* initial RAM */
+#define CFG_SYS_FSL_OCRAM_BASE         0x10000000 /* initial RAM */
 #define SYS_FSL_OCRAM_SPACE_SIZE               0x00200000 /* 2M space */
-#define CONFIG_SYS_FSL_OCRAM_SIZE              0x00020000 /* Real size 128K */
+#define CFG_SYS_FSL_OCRAM_SIZE         0x00020000 /* Real size 128K */
 
 #define DCSR_DCFG_SBEESR2                      0x20140534
 #define DCSR_DCFG_MBEESR2                      0x20140544
 
-#define CONFIG_SYS_FSL_WDOG_BE
-#define CONFIG_SYS_FSL_DSPI_BE
-
 /* SoC related */
 #ifdef CONFIG_ARCH_LS1043A
-#define CONFIG_SYS_FSL_QMAN_V3
 #define CONFIG_SYS_NUM_FMAN                    1
 #define CONFIG_SYS_NUM_FM1_DTSEC               7
 #define CONFIG_SYS_NUM_FM1_10GEC               1
@@ -263,17 +248,13 @@
 #define GIC_ADDR_BIT           31
 #define SCFG_GIC400_ALIGN      0x1570188
 
-#define CONFIG_SYS_FSL_MAX_NUM_OF_SEC          1
-
 #elif defined(CONFIG_ARCH_LS1012A)
 #define GICD_BASE              0x01401000
 #define GICC_BASE              0x01402000
-#define CONFIG_SYS_FSL_MAX_NUM_OF_SEC           1
 #define CONFIG_SYS_DDR_BLOCK1_SIZE     ((phys_size_t)2 << 30)
 #define CONFIG_MAX_MEM_MAPPED          CONFIG_SYS_DDR_BLOCK1_SIZE
 
 #elif defined(CONFIG_ARCH_LS1046A)
-#define CONFIG_SYS_FSL_QMAN_V3
 #define CONFIG_SYS_NUM_FMAN                    1
 #define CONFIG_SYS_NUM_FM1_DTSEC               8
 #define CONFIG_SYS_NUM_FM1_10GEC               2
@@ -286,8 +267,6 @@
 /* Generic Interrupt Controller Definitions */
 #define GICD_BASE              0x01410000
 #define GICC_BASE              0x01420000
-
-#define CONFIG_SYS_FSL_MAX_NUM_OF_SEC          1
 #else
 #error SoC not defined
 #endif