driver/ddr/fsl: Add workaround for A009663

[platform/kernel/u-boot.git] / arch / arm / include / asm / arch-fsl-layerscape / config.h

diff --git a/arch/arm/include/asm/arch-fsl-layerscape/config.h b/arch/arm/include/asm/arch-fsl-layerscape/config.h
index 87bb937..f1b164f 100644 (file)
--- a/arch/arm/include/asm/arch-fsl-layerscape/config.h
+++ b/arch/arm/include/asm/arch-fsl-layerscape/config.h
@@ -17,10 +17,22 @@
 #define CONFIG_SYS_FSL_DDR             /* Freescale DDR driver */
 #define CONFIG_SYS_FSL_DDR_VER         FSL_DDR_VER_5_0
 
-#if defined(CONFIG_LS2085A)
+/*
+ * Reserve secure memory
+ * To be aligned with MMU block size
+ */
+#define CONFIG_SYS_MEM_RESERVE_SECURE  (2048 * 1024)   /* 2MB */
+
+#if defined(CONFIG_LS2080A) || defined(CONFIG_LS2085A)
 #define CONFIG_MAX_CPUS                                16
 #define CONFIG_SYS_FSL_IFC_BANK_COUNT          8
+#ifdef CONFIG_LS2080A
+#define CONFIG_NUM_DDR_CONTROLLERS             2
+#endif
+#ifdef CONFIG_LS2085A
 #define CONFIG_NUM_DDR_CONTROLLERS             3
+#define CONFIG_SYS_FSL_HAS_DP_DDR
+#endif
 #define CONFIG_SYS_FSL_CLUSTER_CLOCKS          { 1, 1, 4, 4 }
 #define        SRDS_MAX_LANES  8
 #define CONFIG_SYS_FSL_SRDS_1
@@ -44,6 +56,7 @@
 #define CONFIG_SYS_FSL_CCSR_SCFG_LE
 #define CONFIG_SYS_FSL_ESDHC_LE
 #define CONFIG_SYS_FSL_IFC_LE
+#define CONFIG_SYS_FSL_PEX_LUT_LE
 
 #define CONFIG_SYS_MEMAC_LITTLE_ENDIAN
 
@@ -60,6 +73,13 @@
 #define CCI_MN_DVM_DOMAIN_CTL          0x200
 #define CCI_MN_DVM_DOMAIN_CTL_SET      0x210
 
+#define CCI_HN_F_0_BASE                        (CCI_MN_BASE + 0x200000)
+#define CCI_HN_F_1_BASE                        (CCI_MN_BASE + 0x210000)
+#define CCN_HN_F_SAM_CTL               0x8     /* offset on base HN_F base */
+#define CCN_HN_F_SAM_NODEID_MASK       0x7f
+#define CCN_HN_F_SAM_NODEID_DDR0       0x4
+#define CCN_HN_F_SAM_NODEID_DDR1       0xe
+
 #define CCI_RN_I_0_BASE                        (CCI_MN_BASE + 0x800000)
 #define CCI_RN_I_2_BASE                        (CCI_MN_BASE + 0x820000)
 #define CCI_RN_I_6_BASE                        (CCI_MN_BASE + 0x860000)
@@ -84,11 +104,23 @@
 #define TZPCDECPROT_2_SET_BASE                 (TZPC_BASE + 0x81C)
 #define TZPCDECPROT_2_CLR_BASE                 (TZPC_BASE + 0x820)
 
+#define DCSR_CGACRE5           0x700070914ULL
+#define EPU_EPCMPR5            0x700060914ULL
+#define EPU_EPCCR5             0x700060814ULL
+#define EPU_EPSMCR5            0x700060228ULL
+#define EPU_EPECR5             0x700060314ULL
+#define EPU_EPCTR5             0x700060a14ULL
+#define EPU_EPGCR              0x700060000ULL
+
 #define CONFIG_SYS_FSL_ERRATUM_A008336
 #define CONFIG_SYS_FSL_ERRATUM_A008511
 #define CONFIG_SYS_FSL_ERRATUM_A008514
 #define CONFIG_SYS_FSL_ERRATUM_A008585
 #define CONFIG_SYS_FSL_ERRATUM_A008751
+#define CONFIG_SYS_FSL_ERRATUM_A009635
+#define CONFIG_SYS_FSL_ERRATUM_A009663
+#define CONFIG_SYS_FSL_ERRATUM_A009942
+
 #elif defined(CONFIG_LS1043A)
 #define CONFIG_MAX_CPUS                                4
 #define CONFIG_SYS_CACHELINE_SIZE              64
@@ -103,8 +135,8 @@
 #define CONFIG_SYS_FSL_OCRAM_BASE              0x10000000 /* initial RAM */
 #define CONFIG_SYS_FSL_OCRAM_SIZE              0x200000 /* 2 MiB */
 #define CONFIG_SYS_FSL_DDR_BE
-#define CONFIG_SYS_LS1_DDR_BLOCK1_SIZE  ((phys_size_t)2 << 30)
-#define CONFIG_MAX_MEM_MAPPED           CONFIG_SYS_LS1_DDR_BLOCK1_SIZE
+#define CONFIG_SYS_DDR_BLOCK1_SIZE             ((phys_size_t)2 << 30)
+#define CONFIG_MAX_MEM_MAPPED                  CONFIG_SYS_DDR_BLOCK1_SIZE
 
 #define CONFIG_SYS_FSL_CCSR_GUR_BE
 #define CONFIG_SYS_FSL_CCSR_SCFG_BE
@@ -113,6 +145,7 @@
 #define CONFIG_SYS_FSL_WDOG_BE
 #define CONFIG_SYS_FSL_DSPI_BE
 #define CONFIG_SYS_FSL_QSPI_BE
+#define CONFIG_SYS_FSL_PEX_LUT_BE
 
 #define QE_MURAM_SIZE          0x6000UL
 #define MAX_QE_RISC            1
@@ -123,8 +156,8 @@
 #define CONFIG_SYS_FSL_PCIE_COMPAT             "fsl,qoriq-pcie-v2.4"
 
 #define CONFIG_SYS_FSL_SFP_VER_3_2
-#define CONFIG_SYS_FSL_SNVS_LE
-#define CONFIG_SYS_FSL_SEC_LE
+#define CONFIG_SYS_FSL_SEC_MON_BE
+#define CONFIG_SYS_FSL_SEC_BE
 #define CONFIG_SYS_FSL_SFP_BE
 #define CONFIG_SYS_FSL_SRK_LE
 #define CONFIG_KEY_REVOCATION
@@ -136,6 +169,8 @@
 #define GICD_BASE              0x01401000
 #define GICC_BASE              0x01402000
 
+#define CONFIG_SYS_FSL_ERRATUM_A009663
+#define CONFIG_SYS_FSL_ERRATUM_A009929
 #else
 #error SoC not defined
 #endif