* To be aligned with MMU block size
*/
#define CONFIG_SYS_MEM_RESERVE_SECURE (2048 * 1024) /* 2MB */
+#define SPL_TLB_SETBACK 0x1000000 /* 16MB under effective memory top */
-#ifdef CONFIG_LS2080A
+#ifdef CONFIG_ARCH_LS2080A
#define CONFIG_SYS_FSL_CLUSTER_CLOCKS { 1, 1, 4, 4 }
#define SRDS_MAX_LANES 8
#define CONFIG_SYS_PAGE_SIZE 0x10000
#define CONFIG_SYS_FSL_PEX_LUT_BE
/* SoC related */
-#ifdef CONFIG_LS1043A
+#ifdef CONFIG_ARCH_LS1043A
#define CONFIG_SYS_FMAN_V3
#define CONFIG_SYS_NUM_FMAN 1
#define CONFIG_SYS_NUM_FM1_DTSEC 7