Merge branch 'master' of git://git.denx.de/u-boot-spi

[platform/kernel/u-boot.git] / arch / arm / include / asm / arch-exynos / cpu.h

diff --git a/arch/arm/include/asm/arch-exynos/cpu.h b/arch/arm/include/asm/arch-exynos/cpu.h
index f06af2e..36b98c8 100644 (file)
--- a/arch/arm/include/asm/arch-exynos/cpu.h
+++ b/arch/arm/include/asm/arch-exynos/cpu.h
@@ -27,7 +27,7 @@
 #define EXYNOS_CPU_NAME                        "Exynos"
 #define EXYNOS4_ADDR_BASE              0x10000000
 
-/* EXYNOS4 */
+/* EXYNOS4 Common*/
 #define EXYNOS4_I2C_SPACING            0x10000
 
 #define EXYNOS4_GPIO_PART3_BASE                0x03860000
@@ -38,6 +38,7 @@
 #define EXYNOS4_CLOCK_BASE             0x10030000
 #define EXYNOS4_SYSTIMER_BASE          0x10050000
 #define EXYNOS4_WATCHDOG_BASE          0x10060000
+#define EXYNOS4_TZPC_BASE              0x10110000
 #define EXYNOS4_MIU_BASE               0x10600000
 #define EXYNOS4_DMC0_BASE              0x10400000
 #define EXYNOS4_DMC1_BASE              0x10410000
@@ -62,8 +63,44 @@
 #define EXYNOS4_GPIO_PART4_BASE                DEVICE_NOT_AVAILABLE
 #define EXYNOS4_DP_BASE                        DEVICE_NOT_AVAILABLE
 #define EXYNOS4_SPI_ISP_BASE           DEVICE_NOT_AVAILABLE
-
-/* EXYNOS5 */
+#define EXYNOS4_ACE_SFR_BASE           DEVICE_NOT_AVAILABLE
+
+/* EXYNOS4X12 */
+#define EXYNOS4X12_GPIO_PART3_BASE     0x03860000
+#define EXYNOS4X12_PRO_ID              0x10000000
+#define EXYNOS4X12_SYSREG_BASE         0x10010000
+#define EXYNOS4X12_POWER_BASE          0x10020000
+#define EXYNOS4X12_SWRESET             0x10020400
+#define EXYNOS4X12_USBPHY_CONTROL      0x10020704
+#define EXYNOS4X12_CLOCK_BASE          0x10030000
+#define EXYNOS4X12_SYSTIMER_BASE       0x10050000
+#define EXYNOS4X12_WATCHDOG_BASE       0x10060000
+#define EXYNOS4X12_TZPC_BASE           0x10110000
+#define EXYNOS4X12_DMC0_BASE           0x10600000
+#define EXYNOS4X12_DMC1_BASE           0x10610000
+#define EXYNOS4X12_GPIO_PART4_BASE     0x106E0000
+#define EXYNOS4X12_GPIO_PART2_BASE     0x11000000
+#define EXYNOS4X12_GPIO_PART1_BASE     0x11400000
+#define EXYNOS4X12_FIMD_BASE           0x11C00000
+#define EXYNOS4X12_MIPI_DSIM_BASE      0x11C80000
+#define EXYNOS4X12_USBOTG_BASE         0x12480000
+#define EXYNOS4X12_MMC_BASE            0x12510000
+#define EXYNOS4X12_SROMC_BASE          0x12570000
+#define EXYNOS4X12_USB_HOST_EHCI_BASE  0x12580000
+#define EXYNOS4X12_USBPHY_BASE         0x125B0000
+#define EXYNOS4X12_UART_BASE           0x13800000
+#define EXYNOS4X12_I2C_BASE            0x13860000
+#define EXYNOS4X12_PWMTIMER_BASE       0x139D0000
+
+#define EXYNOS4X12_ADC_BASE            DEVICE_NOT_AVAILABLE
+#define EXYNOS4X12_DP_BASE             DEVICE_NOT_AVAILABLE
+#define EXYNOS4X12_MODEM_BASE          DEVICE_NOT_AVAILABLE
+#define EXYNOS4X12_I2S_BASE            DEVICE_NOT_AVAILABLE
+#define EXYNOS4X12_SPI_BASE            DEVICE_NOT_AVAILABLE
+#define EXYNOS4X12_SPI_ISP_BASE                DEVICE_NOT_AVAILABLE
+#define EXYNOS4X12_ACE_SFR_BASE                DEVICE_NOT_AVAILABLE
+
+/* EXYNOS5 Common*/
 #define EXYNOS5_I2C_SPACING            0x10000
 
 #define EXYNOS5_GPIO_PART4_BASE                0x03860000
@@ -72,7 +109,9 @@
 #define EXYNOS5_POWER_BASE             0x10040000
 #define EXYNOS5_SWRESET                        0x10040400
 #define EXYNOS5_SYSREG_BASE            0x10050000
+#define EXYNOS5_TZPC_BASE              0x10100000
 #define EXYNOS5_WATCHDOG_BASE          0x101D0000
+#define EXYNOS5_ACE_SFR_BASE            0x10830000
 #define EXYNOS5_DMC_PHY0_BASE          0x10C00000
 #define EXYNOS5_DMC_PHY1_BASE          0x10C10000
 #define EXYNOS5_GPIO_PART3_BASE                0x10D10000
@@ -154,21 +193,25 @@ static inline int proid_is_##type(void)                   \
 }
 
 IS_EXYNOS_TYPE(exynos4210, 0x4210)
+IS_EXYNOS_TYPE(exynos4412, 0x4412)
 IS_EXYNOS_TYPE(exynos5250, 0x5250)
 
 #define SAMSUNG_BASE(device, base)                             \
 static inline unsigned int samsung_get_base_##device(void)     \
 {                                                              \
-       if (cpu_is_exynos4())                                   \
+       if (cpu_is_exynos4()) {                                 \
+               if (proid_is_exynos4412())                      \
+                       return EXYNOS4X12_##base;               \
                return EXYNOS4_##base;                          \
-       else if (cpu_is_exynos5())                              \
+       } else if (cpu_is_exynos5()) {                          \
                return EXYNOS5_##base;                          \
-       else                                                    \
-               return 0;                                       \
+       }                                                       \
+       return 0;                                               \
 }
 
 SAMSUNG_BASE(adc, ADC_BASE)
 SAMSUNG_BASE(clock, CLOCK_BASE)
+SAMSUNG_BASE(ace_sfr, ACE_SFR_BASE)
 SAMSUNG_BASE(dp, DP_BASE)
 SAMSUNG_BASE(sysreg, SYSREG_BASE)
 SAMSUNG_BASE(fimd, FIMD_BASE)
@@ -193,6 +236,7 @@ SAMSUNG_BASE(watchdog, WATCHDOG_BASE)
 SAMSUNG_BASE(power, POWER_BASE)
 SAMSUNG_BASE(spi, SPI_BASE)
 SAMSUNG_BASE(spi_isp, SPI_ISP_BASE)
+SAMSUNG_BASE(tzpc, TZPC_BASE)
 #endif
 
 #endif /* _EXYNOS4_CPU_H */