include/asm/arch-at91: update several .h files to ATMEL_xxx name scheme

[kernel/u-boot.git] / arch / arm / include / asm / arch-at91 / at91sam9_sdramc.h

diff --git a/arch/arm/include/asm/arch-at91/at91sam9_sdramc.h b/arch/arm/include/asm/arch-at91/at91sam9_sdramc.h
index c3da3a6..54159a7 100644 (file)
--- a/arch/arm/include/asm/arch-at91/at91sam9_sdramc.h
+++ b/arch/arm/include/asm/arch-at91/at91sam9_sdramc.h
@@ -19,19 +19,19 @@
 
 #ifdef __ASSEMBLY__
 
-#ifndef AT91_SDRAMC_BASE
-#define AT91_SDRAMC_BASE       AT91_SDRAMC0_BASE
+#ifndef ATMEL_BASE_SDRAMC
+#define ATMEL_BASE_SDRAMC      AT91_SDRAMC0_BASE
 #endif
 
-#define AT91_ASM_SDRAMC_MR     AT91_SDRAMC_BASE
-#define AT91_ASM_SDRAMC_TR     (AT91_SDRAMC_BASE + 0x04)
-#define AT91_ASM_SDRAMC_CR     (AT91_SDRAMC_BASE + 0x08)
-#define AT91_ASM_SDRAMC_MDR    (AT91_SDRAMC_BASE + 0x24)
+#define AT91_ASM_SDRAMC_MR     ATMEL_BASE_SDRAMC
+#define AT91_ASM_SDRAMC_TR     (ATMEL_BASE_SDRAMC + 0x04)
+#define AT91_ASM_SDRAMC_CR     (ATMEL_BASE_SDRAMC + 0x08)
+#define AT91_ASM_SDRAMC_MDR    (ATMEL_BASE_SDRAMC + 0x24)
 
 #endif
 
 /* SDRAM Controller (SDRAMC) registers */
-#define AT91_SDRAMC_MR         (AT91_SDRAMC + 0x00)    /* SDRAM Controller Mode Register */
+#define AT91_SDRAMC_MR         (ATMEL_BASE_SDRAMC + 0x00)      /* SDRAM Controller Mode Register */
 #define                AT91_SDRAMC_MODE        (0xf << 0)              /* Command Mode */
 #define                        AT91_SDRAMC_MODE_NORMAL         0
 #define                        AT91_SDRAMC_MODE_NOP            1
@@ -41,10 +41,10 @@
 #define                        AT91_SDRAMC_MODE_EXT_LMR        5
 #define                        AT91_SDRAMC_MODE_DEEP           6
 
-#define AT91_SDRAMC_TR         (AT91_SDRAMC + 0x04)    /* SDRAM Controller Refresh Timer Register */
+#define AT91_SDRAMC_TR         (ATMEL_BASE_SDRAMC + 0x04)      /* SDRAM Controller Refresh Timer Register */
 #define                AT91_SDRAMC_COUNT       (0xfff << 0)            /* Refresh Timer Counter */
 
-#define AT91_SDRAMC_CR         (AT91_SDRAMC + 0x08)    /* SDRAM Controller Configuration Register */
+#define AT91_SDRAMC_CR         (ATMEL_BASE_SDRAMC + 0x08)      /* SDRAM Controller Configuration Register */
 #define                AT91_SDRAMC_NC          (3 << 0)                /* Number of Column Bits */
 #define                        AT91_SDRAMC_NC_8        (0 << 0)
 #define                        AT91_SDRAMC_NC_9        (1 << 0)
@@ -71,7 +71,7 @@
 #define                AT91_SDRAMC_TRAS        (0xf << 24)             /* Active to Precharge Delay */
 #define                AT91_SDRAMC_TXSR        (0xf << 28)             /* Exit Self Refresh to Active Delay */
 
-#define AT91_SDRAMC_LPR                (AT91_SDRAMC + 0x10)    /* SDRAM Controller Low Power Register */
+#define AT91_SDRAMC_LPR                (ATMEL_BASE_SDRAMC + 0x10)      /* SDRAM Controller Low Power Register */
 #define                AT91_SDRAMC_LPCB                (3 << 0)        /* Low-power Configurations */
 #define                        AT91_SDRAMC_LPCB_DISABLE                0
 #define                        AT91_SDRAMC_LPCB_SELF_REFRESH           1
@@ -85,13 +85,13 @@
 #define                        AT91_SDRAMC_TIMEOUT_64_CLK_CYCLES       (1 << 12)
 #define                        AT91_SDRAMC_TIMEOUT_128_CLK_CYCLES      (2 << 12)
 
-#define AT91_SDRAMC_IER                (AT91_SDRAMC + 0x14)    /* SDRAM Controller Interrupt Enable Register */
-#define AT91_SDRAMC_IDR                (AT91_SDRAMC + 0x18)    /* SDRAM Controller Interrupt Disable Register */
-#define AT91_SDRAMC_IMR                (AT91_SDRAMC + 0x1C)    /* SDRAM Controller Interrupt Mask Register */
-#define AT91_SDRAMC_ISR                (AT91_SDRAMC + 0x20)    /* SDRAM Controller Interrupt Status Register */
+#define AT91_SDRAMC_IER                (ATMEL_BASE_SDRAMC + 0x14)      /* SDRAM Controller Interrupt Enable Register */
+#define AT91_SDRAMC_IDR                (ATMEL_BASE_SDRAMC + 0x18)      /* SDRAM Controller Interrupt Disable Register */
+#define AT91_SDRAMC_IMR                (ATMEL_BASE_SDRAMC + 0x1C)      /* SDRAM Controller Interrupt Mask Register */
+#define AT91_SDRAMC_ISR                (ATMEL_BASE_SDRAMC + 0x20)      /* SDRAM Controller Interrupt Status Register */
 #define                AT91_SDRAMC_RES         (1 << 0)                /* Refresh Error Status */
 
-#define AT91_SDRAMC_MDR                (AT91_SDRAMC + 0x24)    /* SDRAM Memory Device Register */
+#define AT91_SDRAMC_MDR                (ATMEL_BASE_SDRAMC + 0x24)      /* SDRAM Memory Device Register */
 #define                AT91_SDRAMC_MD          (3 << 0)                /* Memory Device Type */
 #define                        AT91_SDRAMC_MD_SDRAM            0
 #define                        AT91_SDRAMC_MD_LOW_POWER_SDRAM  1