/* Micron MT41K256M16HA-125E */
#define MT41K256M16HA125E_EMIF_READ_LATENCY 0x100007
#define MT41K256M16HA125E_EMIF_TIM1 0x0AAAD4DB
-#define MT41K256M16HA125E_EMIF_TIM2 0x26437FDA
-#define MT41K256M16HA125E_EMIF_TIM3 0x501F83FF
-#define MT41K256M16HA125E_EMIF_SDCFG 0x61C052B2
+#define MT41K256M16HA125E_EMIF_TIM2 0x266B7FDA
+#define MT41K256M16HA125E_EMIF_TIM3 0x501F867F
+#define MT41K256M16HA125E_EMIF_SDCFG 0x61C05332
#define MT41K256M16HA125E_EMIF_SDREF 0xC30
#define MT41K256M16HA125E_ZQ_CFG 0x50074BE4
#define MT41K256M16HA125E_DLL_LOCK_DIFF 0x1
#define MT41K256M16HA125E_RATIO 0x80
#define MT41K256M16HA125E_INVERT_CLKOUT 0x0
-#define MT41K256M16HA125E_RD_DQS 0x3A
-#define MT41K256M16HA125E_WR_DQS 0x42
-#define MT41K256M16HA125E_PHY_WR_DATA 0x7E
-#define MT41K256M16HA125E_PHY_FIFO_WE 0x9B
+#define MT41K256M16HA125E_RD_DQS 0x38
+#define MT41K256M16HA125E_WR_DQS 0x44
+#define MT41K256M16HA125E_PHY_WR_DATA 0x7D
+#define MT41K256M16HA125E_PHY_FIFO_WE 0x94
#define MT41K256M16HA125E_IOCTRL_VALUE 0x18B
/* Micron MT41J512M8RH-125 on EVM v1.5 */
#define MT41J512M8RH125_PHY_WR_DATA 0x74
#define MT41J512M8RH125_IOCTRL_VALUE 0x18B
+/* Samsung K4B2G1646E-BIH9 */
+#define K4B2G1646EBIH9_EMIF_READ_LATENCY 0x06
+#define K4B2G1646EBIH9_EMIF_TIM1 0x0888A39B
+#define K4B2G1646EBIH9_EMIF_TIM2 0x2A04011A
+#define K4B2G1646EBIH9_EMIF_TIM3 0x501F820F
+#define K4B2G1646EBIH9_EMIF_SDCFG 0x61C24AB2
+#define K4B2G1646EBIH9_EMIF_SDREF 0x0000093B
+#define K4B2G1646EBIH9_ZQ_CFG 0x50074BE4
+#define K4B2G1646EBIH9_DLL_LOCK_DIFF 0x1
+#define K4B2G1646EBIH9_RATIO 0x40
+#define K4B2G1646EBIH9_INVERT_CLKOUT 0x1
+#define K4B2G1646EBIH9_RD_DQS 0x3B
+#define K4B2G1646EBIH9_WR_DQS 0x85
+#define K4B2G1646EBIH9_PHY_FIFO_WE 0x100
+#define K4B2G1646EBIH9_PHY_WR_DATA 0xC1
+#define K4B2G1646EBIH9_IOCTRL_VALUE 0x18B
+
/**
* Configure DMM
*/
* This structure represents the DDR io control on AM33XX devices.
*/
struct ddr_cmdtctrl {
- unsigned int resv1[1];
unsigned int cm0ioctl;
unsigned int cm1ioctl;
unsigned int cm2ioctl;