Merge branch 'master' of git://git.denx.de/u-boot-samsung

[platform/kernel/u-boot.git] / arch / arm / include / asm / arch-am33xx / ddr_defs.h

diff --git a/arch/arm/include/asm/arch-am33xx/ddr_defs.h b/arch/arm/include/asm/arch-am33xx/ddr_defs.h
index 2278358..a97ebb5 100644 (file)
--- a/arch/arm/include/asm/arch-am33xx/ddr_defs.h
+++ b/arch/arm/include/asm/arch-am33xx/ddr_defs.h
@@ -18,7 +18,11 @@
 #define VTP_CTRL_READY         (0x1 << 5)
 #define VTP_CTRL_ENABLE                (0x1 << 6)
 #define VTP_CTRL_START_EN      (0x1)
+#ifdef CONFIG_AM43XX
+#define DDR_CKE_CTRL_NORMAL    0x3
+#else
 #define DDR_CKE_CTRL_NORMAL    0x1
+#endif
 #define PHY_EN_DYN_PWRDN       (0x1 << 20)
 
 /* Micron MT47H128M16RT-25E */
@@ -29,17 +33,13 @@
 #define MT47H128M16RT25E_EMIF_SDCFG            0x41805332
 #define MT47H128M16RT25E_EMIF_SDREF            0x0000081a
 #define MT47H128M16RT25E_RATIO                 0x80
-#define MT47H128M16RT25E_INVERT_CLKOUT         0x00
 #define MT47H128M16RT25E_RD_DQS                        0x12
-#define MT47H128M16RT25E_WR_DQS                        0x00
-#define MT47H128M16RT25E_PHY_WRLVL             0x00
-#define MT47H128M16RT25E_PHY_GATELVL           0x00
 #define MT47H128M16RT25E_PHY_WR_DATA           0x40
 #define MT47H128M16RT25E_PHY_FIFO_WE           0x80
 #define MT47H128M16RT25E_IOCTRL_VALUE          0x18B
 
 /* Micron MT41J128M16JT-125 */
-#define MT41J128MJT125_EMIF_READ_LATENCY       0x06
+#define MT41J128MJT125_EMIF_READ_LATENCY       0x100006
 #define MT41J128MJT125_EMIF_TIM1               0x0888A39B
 #define MT41J128MJT125_EMIF_TIM2               0x26337FDA
 #define MT41J128MJT125_EMIF_TIM3               0x501F830F
@@ -54,6 +54,37 @@
 #define MT41J128MJT125_PHY_FIFO_WE             0x100
 #define MT41J128MJT125_IOCTRL_VALUE            0x18B
 
+/* Micron MT41J128M16JT-125 at 400MHz*/
+#define MT41J128MJT125_EMIF_READ_LATENCY_400MHz        0x100007
+#define MT41J128MJT125_EMIF_TIM1_400MHz                0x0AAAD4DB
+#define MT41J128MJT125_EMIF_TIM2_400MHz                0x26437FDA
+#define MT41J128MJT125_EMIF_TIM3_400MHz                0x501F83FF
+#define MT41J128MJT125_EMIF_SDCFG_400MHz       0x61C052B2
+#define MT41J128MJT125_EMIF_SDREF_400MHz       0x00000C30
+#define MT41J128MJT125_ZQ_CFG_400MHz           0x50074BE4
+#define MT41J128MJT125_RATIO_400MHz            0x80
+#define MT41J128MJT125_INVERT_CLKOUT_400MHz    0x0
+#define MT41J128MJT125_RD_DQS_400MHz           0x3A
+#define MT41J128MJT125_WR_DQS_400MHz           0x3B
+#define MT41J128MJT125_PHY_WR_DATA_400MHz      0x76
+#define MT41J128MJT125_PHY_FIFO_WE_400MHz      0x96
+
+/* Micron MT41K128M16JT-187E */
+#define MT41K128MJT187E_EMIF_READ_LATENCY      0x06
+#define MT41K128MJT187E_EMIF_TIM1              0x0888B3DB
+#define MT41K128MJT187E_EMIF_TIM2              0x36337FDA
+#define MT41K128MJT187E_EMIF_TIM3              0x501F830F
+#define MT41K128MJT187E_EMIF_SDCFG             0x61C04AB2
+#define MT41K128MJT187E_EMIF_SDREF             0x0000093B
+#define MT41K128MJT187E_ZQ_CFG                 0x50074BE4
+#define MT41K128MJT187E_RATIO                  0x40
+#define MT41K128MJT187E_INVERT_CLKOUT          0x1
+#define MT41K128MJT187E_RD_DQS                 0x3B
+#define MT41K128MJT187E_WR_DQS                 0x85
+#define MT41K128MJT187E_PHY_WR_DATA            0xC1
+#define MT41K128MJT187E_PHY_FIFO_WE            0x100
+#define MT41K128MJT187E_IOCTRL_VALUE           0x18B
+
 /* Micron MT41J64M16JT-125 */
 #define MT41J64MJT125_EMIF_SDCFG               0x61C04A32
 
@@ -61,7 +92,7 @@
 #define MT41J256MJT125_EMIF_SDCFG              0x61C04B32
 
 /* Micron MT41J256M8HX-15E */
-#define MT41J256M8HX15E_EMIF_READ_LATENCY      0x06
+#define MT41J256M8HX15E_EMIF_READ_LATENCY      0x100006
 #define MT41J256M8HX15E_EMIF_TIM1              0x0888A39B
 #define MT41J256M8HX15E_EMIF_TIM2              0x26337FDA
 #define MT41J256M8HX15E_EMIF_TIM3              0x501F830F
@@ -93,7 +124,7 @@
 #define MT41K256M16HA125E_IOCTRL_VALUE         0x18B
 
 /* Micron MT41J512M8RH-125 on EVM v1.5 */
-#define MT41J512M8RH125_EMIF_READ_LATENCY      0x06
+#define MT41J512M8RH125_EMIF_READ_LATENCY      0x100006
 #define MT41J512M8RH125_EMIF_TIM1              0x0888A39B
 #define MT41J512M8RH125_EMIF_TIM2              0x26517FDA
 #define MT41J512M8RH125_EMIF_TIM3              0x501F84EF
@@ -109,7 +140,7 @@
 #define MT41J512M8RH125_IOCTRL_VALUE           0x18B
 
 /* Samsung K4B2G1646E-BIH9 */
-#define K4B2G1646EBIH9_EMIF_READ_LATENCY       0x07
+#define K4B2G1646EBIH9_EMIF_READ_LATENCY       0x100007
 #define K4B2G1646EBIH9_EMIF_TIM1               0x0AAAE51B
 #define K4B2G1646EBIH9_EMIF_TIM2               0x2A1D7FDA
 #define K4B2G1646EBIH9_EMIF_TIM3               0x501F83FF
@@ -124,6 +155,22 @@
 #define K4B2G1646EBIH9_PHY_WR_DATA             0x76
 #define K4B2G1646EBIH9_IOCTRL_VALUE            0x18B
 
+#define  LPDDR2_ADDRCTRL_IOCTRL_VALUE   0x294
+#define  LPDDR2_ADDRCTRL_WD0_IOCTRL_VALUE 0x00000000
+#define  LPDDR2_ADDRCTRL_WD1_IOCTRL_VALUE 0x00000000
+#define  LPDDR2_DATA0_IOCTRL_VALUE   0x20000294
+#define  LPDDR2_DATA1_IOCTRL_VALUE   0x20000294
+#define  LPDDR2_DATA2_IOCTRL_VALUE   0x20000294
+#define  LPDDR2_DATA3_IOCTRL_VALUE   0x20000294
+
+#define  DDR3_ADDRCTRL_WD0_IOCTRL_VALUE 0x00000000
+#define  DDR3_ADDRCTRL_WD1_IOCTRL_VALUE 0x00000000
+#define  DDR3_ADDRCTRL_IOCTRL_VALUE   0x84
+#define  DDR3_DATA0_IOCTRL_VALUE   0x84
+#define  DDR3_DATA1_IOCTRL_VALUE   0x84
+#define  DDR3_DATA2_IOCTRL_VALUE   0x84
+#define  DDR3_DATA3_IOCTRL_VALUE   0x84
+
 /**
  * Configure DMM
  */
@@ -133,6 +180,7 @@ void config_dmm(const struct dmm_lisa_map_regs *regs);
  * Configure SDRAM
  */
 void config_sdram(const struct emif_regs *regs, int nr);
+void config_sdram_emif4d5(const struct emif_regs *regs, int nr);
 
 /**
  * Set SDRAM timings
@@ -278,12 +326,27 @@ struct ddr_cmdtctrl {
        unsigned int resv2[12];
        unsigned int dt0ioctl;
        unsigned int dt1ioctl;
+       unsigned int dt2ioctrl;
+       unsigned int dt3ioctrl;
+       unsigned int resv3[4];
+       unsigned int emif_sdram_config_ext;
+};
+
+struct ctrl_ioregs {
+       unsigned int cm0ioctl;
+       unsigned int cm1ioctl;
+       unsigned int cm2ioctl;
+       unsigned int dt0ioctl;
+       unsigned int dt1ioctl;
+       unsigned int dt2ioctrl;
+       unsigned int dt3ioctrl;
+       unsigned int emif_sdram_config_ext;
 };
 
 /**
  * Configure DDR io control registers
  */
-void config_io_ctrl(unsigned long val);
+void config_io_ctrl(const struct ctrl_ioregs *ioregs);
 
 struct ddr_ctrl {
        unsigned int ddrioctrl;
@@ -291,8 +354,15 @@ struct ddr_ctrl {
        unsigned int ddrckectrl;
 };
 
-void config_ddr(unsigned int pll, unsigned int ioctrl,
+#ifdef CONFIG_TI816X
+void config_ddr(const struct ddr_data *data, const struct cmd_control *ctrl,
+               const struct emif_regs *regs,
+               const struct dmm_lisa_map_regs *lisa_regs, int nrs);
+#else
+void config_ddr(unsigned int pll, const struct ctrl_ioregs *ioregs,
                const struct ddr_data *data, const struct cmd_control *ctrl,
                const struct emif_regs *regs, int nr);
+#endif
+void emif_get_ext_phy_ctrl_const_regs(const u32 **regs, u32 *size);
 
 #endif  /* _DDR_DEFS_H */