#include <asm/arch/hardware.h>
-#define BIT(x) (1 << x)
#define CL_BIT(x) (0 << x)
/* Timer register bits */
#define TCLR_PRE BIT(5) /* Pre-scaler enable */
#define TCLR_PTV_SHIFT (2) /* Pre-scaler shift value */
#define TCLR_PRE_DISABLE CL_BIT(5) /* Pre-scalar disable */
-
-/* device type */
-#define DEVICE_MASK (BIT(8) | BIT(9) | BIT(10))
-#define TST_DEVICE 0x0
-#define EMU_DEVICE 0x1
-#define HS_DEVICE 0x2
-#define GP_DEVICE 0x3
-
-/* cpu-id for AM33XX and TI81XX family */
+#define TCLR_CE BIT(6) /* compare mode enable */
+#define TCLR_SCPWM BIT(7) /* pwm outpin behaviour */
+#define TCLR_TCM BIT(8) /* edge detection of input pin*/
+#define TCLR_TRG_SHIFT (10) /* trigmode on pwm outpin */
+#define TCLR_PT BIT(12) /* pulse/toggle mode of outpin*/
+#define TCLR_CAPTMODE BIT(13) /* capture mode */
+#define TCLR_GPOCFG BIT(14) /* 0=output,1=input */
+
+#define TCFG_RESET BIT(0) /* software reset */
+#define TCFG_EMUFREE BIT(1) /* behaviour of tmr on debug */
+#define TCFG_IDLEMOD_SHIFT (2) /* power management */
+
+/* cpu-id for AM43XX AM33XX and TI81XX family */
+#define AM437X 0xB98C
#define AM335X 0xB944
#define TI81XX 0xB81E
#define DEVICE_ID (CTRL_BASE + 0x0600)
#define DEVICE_ID_MASK 0x1FFF
+#define PACKAGE_TYPE_SHIFT 16
+#define PACKAGE_TYPE_MASK (3 << 16)
+
+/* Package Type */
+#define PACKAGE_TYPE_UNDEFINED 0x0
+#define PACKAGE_TYPE_ZCZ 0x1
+#define PACKAGE_TYPE_ZCE 0x2
+#define PACKAGE_TYPE_RESERVED 0x3
/* MPU max frequencies */
#define AM335X_ZCZ_300 0x1FEF
#define PRM_RSTCTRL_RESET 0x01
#define PRM_RSTST_WARM_RESET_MASK 0x232
-/*
- * Watchdog:
- * Using the prescaler, the OMAP watchdog could go for many
- * months before firing. These limits work without scaling,
- * with the 60 second default assumed by most tools and docs.
- */
-#define TIMER_MARGIN_MAX (24 * 60 * 60) /* 1 day */
-#define TIMER_MARGIN_DEFAULT 60 /* 60 secs */
-#define TIMER_MARGIN_MIN 1
-
-#define PTV 0 /* prescale */
-#define GET_WLDR_VAL(secs) (0xffffffff - ((secs) * (32768/(1<<PTV))) + 1)
-#define WDT_WWPS_PEND_WCLR BIT(0)
-#define WDT_WWPS_PEND_WLDR BIT(2)
-#define WDT_WWPS_PEND_WTGR BIT(3)
-#define WDT_WWPS_PEND_WSPR BIT(4)
-
-#define WDT_WCLR_PRE BIT(5)
-#define WDT_WCLR_PTV_OFF 2
-
#ifndef __KERNEL_STRICT_NAMES
#ifndef __ASSEMBLY__
-struct gpmc_cs {
- u32 config1; /* 0x00 */
- u32 config2; /* 0x04 */
- u32 config3; /* 0x08 */
- u32 config4; /* 0x0C */
- u32 config5; /* 0x10 */
- u32 config6; /* 0x14 */
- u32 config7; /* 0x18 */
- u32 nand_cmd; /* 0x1C */
- u32 nand_adr; /* 0x20 */
- u32 nand_dat; /* 0x24 */
- u8 res[8]; /* blow up to 0x30 byte */
-};
-
-struct bch_res_0_3 {
- u32 bch_result_x[4];
-};
-
-struct gpmc {
- u8 res1[0x10];
- u32 sysconfig; /* 0x10 */
- u8 res2[0x4];
- u32 irqstatus; /* 0x18 */
- u32 irqenable; /* 0x1C */
- u8 res3[0x20];
- u32 timeout_control; /* 0x40 */
- u8 res4[0xC];
- u32 config; /* 0x50 */
- u32 status; /* 0x54 */
- u8 res5[0x8]; /* 0x58 */
- struct gpmc_cs cs[8]; /* 0x60, 0x90, .. */
- u8 res6[0x14]; /* 0x1E0 */
- u32 ecc_config; /* 0x1F4 */
- u32 ecc_control; /* 0x1F8 */
- u32 ecc_size_config; /* 0x1FC */
- u32 ecc1_result; /* 0x200 */
- u32 ecc2_result; /* 0x204 */
- u32 ecc3_result; /* 0x208 */
- u32 ecc4_result; /* 0x20C */
- u32 ecc5_result; /* 0x210 */
- u32 ecc6_result; /* 0x214 */
- u32 ecc7_result; /* 0x218 */
- u32 ecc8_result; /* 0x21C */
- u32 ecc9_result; /* 0x220 */
- u8 res7[12]; /* 0x224 */
- u32 testmomde_ctrl; /* 0x230 */
- u8 res8[12]; /* 0x234 */
- struct bch_res_0_3 bch_result_0_3[2]; /* 0x240 */
-};
-
-/* Used for board specific gpmc initialization */
-extern struct gpmc *gpmc_cfg;
+#include <asm/ti-common/omap_wdt.h>
#ifndef CONFIG_AM43XX
/* Encapsulating core pll registers */
unsigned int wkctrlclkctrl; /* offset 0x04 */
unsigned int wkgpio0clkctrl; /* offset 0x08 */
unsigned int wkl4wkclkctrl; /* offset 0x0c */
- unsigned int resv2[4];
+ unsigned int timer0clkctrl; /* offset 0x10 */
+ unsigned int resv2[3];
unsigned int idlestdpllmpu; /* offset 0x20 */
- unsigned int resv3[2];
+ unsigned int sscdeltamstepdllmpu; /* off 0x24 */
+ unsigned int sscmodfreqdivdpllmpu; /* off 0x28 */
unsigned int clkseldpllmpu; /* offset 0x2c */
unsigned int resv4[1];
unsigned int idlestdpllddr; /* offset 0x34 */
unsigned int wkup_uart0ctrl; /* offset 0xB4 */
unsigned int wkup_i2c0ctrl; /* offset 0xB8 */
unsigned int wkup_adctscctrl; /* offset 0xBC */
- unsigned int resv12[6];
+ unsigned int resv12;
+ unsigned int timer1clkctrl; /* offset 0xC4 */
+ unsigned int resv13[4];
unsigned int divm6dpllcore; /* offset 0xD8 */
};
unsigned int epwmss2clkctrl; /* offset 0xD8 */
unsigned int l3instrclkctrl; /* offset 0xDC */
unsigned int l3clkctrl; /* Offset 0xE0 */
- unsigned int resv8[4];
+ unsigned int resv8[2];
+ unsigned int timer5clkctrl; /* offset 0xEC */
+ unsigned int timer6clkctrl; /* offset 0xF0 */
unsigned int mmc1clkctrl; /* offset 0xF4 */
unsigned int mmc2clkctrl; /* offset 0xF8 */
unsigned int resv9[8];
/* Encapsulating Display pll registers */
struct cm_dpll {
- unsigned int resv1[2];
+ unsigned int resv1;
+ unsigned int clktimer7clk; /* offset 0x04 */
unsigned int clktimer2clk; /* offset 0x08 */
- unsigned int resv2[10];
+ unsigned int clktimer3clk; /* offset 0x0C */
+ unsigned int clktimer4clk; /* offset 0x10 */
+ unsigned int resv2;
+ unsigned int clktimer5clk; /* offset 0x18 */
+ unsigned int clktimer6clk; /* offset 0x1C */
+ unsigned int resv3[2];
+ unsigned int clktimer1clk; /* offset 0x28 */
+ unsigned int resv4[2];
unsigned int clklcdcpixelclk; /* offset 0x34 */
};
+
+struct prm_device_inst {
+ unsigned int prm_rstctrl;
+ unsigned int prm_rsttime;
+ unsigned int prm_rstst;
+};
#else
/* Encapsulating core pll registers */
struct cm_wkuppll {
unsigned int resv0[136];
unsigned int wkl4wkclkctrl; /* offset 0x220 */
- unsigned int resv1[55];
+ unsigned int resv1[7];
+ unsigned int usbphy0clkctrl; /* offset 0x240 */
+ unsigned int resv112;
+ unsigned int usbphy1clkctrl; /* offset 0x248 */
+ unsigned int resv113[45];
unsigned int wkclkstctrl; /* offset 0x300 */
unsigned int resv2[15];
unsigned int wkup_i2c0ctrl; /* offset 0x340 */
unsigned int l3clkstctrl; /* offset 0x00 */
unsigned int resv0[7];
unsigned int l3clkctrl; /* Offset 0x20 */
- unsigned int resv1[7];
+ unsigned int resv112[7];
unsigned int l3instrclkctrl; /* offset 0x40 */
unsigned int resv2[3];
unsigned int ocmcramclkctrl; /* offset 0x50 */
unsigned int mcasp1clkctrl; /* offset 0x240 */
unsigned int resv11;
unsigned int mmc2clkctrl; /* offset 0x248 */
- unsigned int resv12[5];
+ unsigned int resv12[3];
+ unsigned int qspiclkctrl; /* offset 0x258 */
+ unsigned int resv121;
unsigned int usb0clkctrl; /* offset 0x260 */
- unsigned int resv13[103];
+ unsigned int resv122;
+ unsigned int usb1clkctrl; /* offset 0x268 */
+ unsigned int resv13[101];
unsigned int l4lsclkstctrl; /* offset 0x400 */
unsigned int resv14[7];
unsigned int l4lsclkctrl; /* offset 0x420 */
unsigned int gpio2clkctrl; /* offset 0x480 */
unsigned int resv20;
unsigned int gpio3clkctrl; /* offset 0x488 */
- unsigned int resv21[7];
+ unsigned int resv41;
+ unsigned int gpio4clkctrl; /* offset 0x490 */
+ unsigned int resv42;
+ unsigned int gpio5clkctrl; /* offset 0x498 */
+ unsigned int resv21[3];
unsigned int i2c1clkctrl; /* offset 0x4A8 */
unsigned int resv22;
unsigned int uart4clkctrl; /* offset 0x598 */
unsigned int resv35;
unsigned int uart5clkctrl; /* offset 0x5A0 */
- unsigned int resv36[87];
+ unsigned int resv36[5];
+ unsigned int usbphyocp2scp0clkctrl; /* offset 0x5B8 */
+ unsigned int resv361;
+ unsigned int usbphyocp2scp1clkctrl; /* offset 0x5C0 */
+ unsigned int resv3611[79];
unsigned int emifclkstctrl; /* offset 0x700 */
- unsigned int resv361[7];
+ unsigned int resv362[7];
unsigned int emifclkctrl; /* offset 0x720 */
unsigned int resv37[3];
unsigned int emiffwclkctrl; /* offset 0x730 */
unsigned int cm_dll_ctrl;
};
+struct prm_device_inst {
+ unsigned int prm_rstctrl;
+ unsigned int prm_rstst;
+};
+
struct cm_dpll {
unsigned int resv1;
unsigned int clktimer2clk; /* offset 0x04 */
+ unsigned int resv2[11];
+ unsigned int clkselmacclk; /* offset 0x34 */
};
#endif /* CONFIG_AM43XX */
unsigned int clkstctrl; /* offset 0x4 */
};
-/* Watchdog timer registers */
-struct wd_timer {
- unsigned int resv1[4];
- unsigned int wdtwdsc; /* offset 0x010 */
- unsigned int wdtwdst; /* offset 0x014 */
- unsigned int wdtwisr; /* offset 0x018 */
- unsigned int wdtwier; /* offset 0x01C */
- unsigned int wdtwwer; /* offset 0x020 */
- unsigned int wdtwclr; /* offset 0x024 */
- unsigned int wdtwcrr; /* offset 0x028 */
- unsigned int wdtwldr; /* offset 0x02C */
- unsigned int wdtwtgr; /* offset 0x030 */
- unsigned int wdtwwps; /* offset 0x034 */
- unsigned int resv2[3];
- unsigned int wdtwdly; /* offset 0x044 */
- unsigned int wdtwspr; /* offset 0x048 */
- unsigned int resv3[1];
- unsigned int wdtwqeoi; /* offset 0x050 */
- unsigned int wdtwqstar; /* offset 0x054 */
- unsigned int wdtwqsta; /* offset 0x058 */
- unsigned int wdtwqens; /* offset 0x05C */
- unsigned int wdtwqenc; /* offset 0x060 */
- unsigned int resv4[39];
- unsigned int wdt_unfr; /* offset 0x100 */
-};
-
/* Timer 32 bit registers */
struct gptimer {
unsigned int tidr; /* offset 0x00 */
#define OMAP_GPIO_SYSSTATUS 0x0114
#define OMAP_GPIO_IRQSTATUS1 0x002c
#define OMAP_GPIO_IRQSTATUS2 0x0030
+#define OMAP_GPIO_IRQSTATUS_SET_0 0x0034
+#define OMAP_GPIO_IRQSTATUS_SET_1 0x0038
#define OMAP_GPIO_CTRL 0x0130
#define OMAP_GPIO_OE 0x0134
#define OMAP_GPIO_DATAIN 0x0138
#define OMAP_GPIO_SETDATAOUT 0x0194
/* Control Device Register */
+
+ /* Control Device Register */
+#define MREQPRIO_0_SAB_INIT1_MASK 0xFFFFFF8F
+#define MREQPRIO_0_SAB_INIT0_MASK 0xFFFFFFF8
+#define MREQPRIO_1_DSS_MASK 0xFFFFFF8F
+
struct ctrl_dev {
unsigned int deviceid; /* offset 0x00 */
unsigned int resv1[7];
unsigned int macid1h; /* offset 0x3c */
unsigned int resv4[4];
unsigned int miisel; /* offset 0x50 */
- unsigned int resv5[106];
+ unsigned int resv5[7];
+ unsigned int mreqprio_0; /* offset 0x70 */
+ unsigned int mreqprio_1; /* offset 0x74 */
+ unsigned int resv6[97];
unsigned int efuse_sma; /* offset 0x1FC */
};
+/* Bandwidth Limiter Portion of the L3Fast Configuration Register */
+#define BW_LIMITER_BW_FRAC_MASK 0xFFFFFFE0
+#define BW_LIMITER_BW_INT_MASK 0xFFFFFFF0
+#define BW_LIMITER_BW_WATERMARK_MASK 0xFFFFF800
+
+struct l3f_cfg_bwlimiter {
+ u32 padding0[2];
+ u32 modena_init0_bw_fractional;
+ u32 modena_init0_bw_integer;
+ u32 modena_init0_watermark_0;
+};
+
/* gmii_sel register defines */
#define GMII1_SEL_MII 0x0
#define GMII1_SEL_RMII 0x1
};
#define ECAP_CLK_EN BIT(0)
#define ECAP_CLK_STOP_REQ BIT(1)
+#define EPWM_CLK_EN BIT(8)
+#define EPWM_CLK_STOP_REQ BIT(9)
struct pwmss_ecap_regs {
unsigned int tsctr;
unsigned short ecctl2;
};
+struct pwmss_epwm_regs {
+ unsigned short tbctl;
+ unsigned short tbsts;
+ unsigned short tbphshr;
+ unsigned short tbphs;
+ unsigned short tbcnt;
+ unsigned short tbprd;
+ unsigned short res1;
+ unsigned short cmpctl;
+ unsigned short cmpahr;
+ unsigned short cmpa;
+ unsigned short cmpb;
+ unsigned short aqctla;
+ unsigned short aqctlb;
+ unsigned short aqsfrc;
+ unsigned short aqcsfrc;
+ unsigned short dbctl;
+ unsigned short dbred;
+ unsigned short dbfed;
+ unsigned short tzsel;
+ unsigned short tzctl;
+ unsigned short tzflg;
+ unsigned short tzclr;
+ unsigned short tzfrc;
+ unsigned short etsel;
+ unsigned short etps;
+ unsigned short etflg;
+ unsigned short etclr;
+ unsigned short etfrc;
+ unsigned short pcctl;
+ unsigned int res2[66];
+ unsigned short hrcnfg;
+};
+
/* Capture Control register 2 */
#define ECTRL2_SYNCOSEL_MASK (0x03 << 6)
#define ECTRL2_MDSL_ECAP BIT(9)
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