/*
* dts file for Xilinx ZynqMP ZCU106
*
- * (C) Copyright 2016, Xilinx, Inc.
+ * (C) Copyright 2016 - 2020, Xilinx, Inc.
*
* Michal Simek <michal.simek@xilinx.com>
*/
label = "sw19";
gpios = <&gpio 22 GPIO_ACTIVE_HIGH>;
linux,code = <KEY_DOWN>;
- gpio-key,wakeup;
+ wakeup-source;
autorepeat;
};
};
leds {
compatible = "gpio-leds";
- heartbeat_led {
+ heartbeat-led {
label = "heartbeat";
gpios = <&gpio 23 GPIO_ACTIVE_HIGH>;
linux,default-trigger = "heartbeat";
ti,rx-internal-delay = <0x8>;
ti,tx-internal-delay = <0xa>;
ti,fifo-depth = <0x1>;
+ ti,dp83867-rxctrl-strap-quirk;
};
};
u76: ina226@40 { /* u76 */
compatible = "ti,ina226";
#io-channel-cells = <1>;
+ label = "ina226-u76";
reg = <0x40>;
shunt-resistor = <5000>;
};
u77: ina226@41 { /* u77 */
compatible = "ti,ina226";
#io-channel-cells = <1>;
+ label = "ina226-u77";
reg = <0x41>;
shunt-resistor = <5000>;
};
u78: ina226@42 { /* u78 */
compatible = "ti,ina226";
#io-channel-cells = <1>;
+ label = "ina226-u78";
reg = <0x42>;
shunt-resistor = <5000>;
};
u87: ina226@43 { /* u87 */
compatible = "ti,ina226";
#io-channel-cells = <1>;
+ label = "ina226-u87";
reg = <0x43>;
shunt-resistor = <5000>;
};
u85: ina226@44 { /* u85 */
compatible = "ti,ina226";
#io-channel-cells = <1>;
+ label = "ina226-u85";
reg = <0x44>;
shunt-resistor = <5000>;
};
u86: ina226@45 { /* u86 */
compatible = "ti,ina226";
#io-channel-cells = <1>;
+ label = "ina226-u86";
reg = <0x45>;
shunt-resistor = <5000>;
};
u93: ina226@46 { /* u93 */
compatible = "ti,ina226";
#io-channel-cells = <1>;
+ label = "ina226-u93";
reg = <0x46>;
shunt-resistor = <5000>;
};
u88: ina226@47 { /* u88 */
compatible = "ti,ina226";
#io-channel-cells = <1>;
+ label = "ina226-u88";
reg = <0x47>;
shunt-resistor = <5000>;
};
u15: ina226@4a { /* u15 */
compatible = "ti,ina226";
#io-channel-cells = <1>;
+ label = "ina226-u15";
reg = <0x4a>;
shunt-resistor = <5000>;
};
u92: ina226@4b { /* u92 */
compatible = "ti,ina226";
#io-channel-cells = <1>;
+ label = "ina226-u92";
reg = <0x4b>;
shunt-resistor = <5000>;
};
u79: ina226@40 { /* u79 */
compatible = "ti,ina226";
#io-channel-cells = <1>;
+ label = "ina226-u79";
reg = <0x40>;
shunt-resistor = <2000>;
};
u81: ina226@41 { /* u81 */
compatible = "ti,ina226";
#io-channel-cells = <1>;
+ label = "ina226-u81";
reg = <0x41>;
shunt-resistor = <5000>;
};
u80: ina226@42 { /* u80 */
compatible = "ti,ina226";
#io-channel-cells = <1>;
+ label = "ina226-u80";
reg = <0x42>;
shunt-resistor = <5000>;
};
u84: ina226@43 { /* u84 */
compatible = "ti,ina226";
#io-channel-cells = <1>;
+ label = "ina226-u84";
reg = <0x43>;
shunt-resistor = <5000>;
};
u16: ina226@44 { /* u16 */
compatible = "ti,ina226";
#io-channel-cells = <1>;
+ label = "ina226-u16";
reg = <0x44>;
shunt-resistor = <5000>;
};
u65: ina226@45 { /* u65 */
compatible = "ti,ina226";
#io-channel-cells = <1>;
+ label = "ina226-u65";
reg = <0x45>;
shunt-resistor = <5000>;
};
u74: ina226@46 { /* u74 */
compatible = "ti,ina226";
#io-channel-cells = <1>;
+ label = "ina226-u74";
reg = <0x46>;
shunt-resistor = <5000>;
};
u75: ina226@47 { /* u75 */
compatible = "ti,ina226";
#io-channel-cells = <1>;
+ label = "ina226-u75";
reg = <0x47>;
shunt-resistor = <5000>;
};
spi-tx-bus-width = <1>;
spi-rx-bus-width = <4>; /* FIXME also DUAL configuration possible */
spi-max-frequency = <108000000>; /* Based on DC1 spec */
- partition@qspi-fsbl-uboot { /* for testing purpose */
+ partition@0 { /* for testing purpose */
label = "qspi-fsbl-uboot";
reg = <0x0 0x100000>;
};
- partition@qspi-linux { /* for testing purpose */
+ partition@100000 { /* for testing purpose */
label = "qspi-linux";
reg = <0x100000 0x500000>;
};
- partition@qspi-device-tree { /* for testing purpose */
+ partition@600000 { /* for testing purpose */
label = "qspi-device-tree";
reg = <0x600000 0x20000>;
};
- partition@qspi-rootfs { /* for testing purpose */
+ partition@620000 { /* for testing purpose */
label = "qspi-rootfs";
reg = <0x620000 0x5E0000>;
};
/* SD1 with level shifter */
&sdhci1 {
status = "okay";
+ /*
+ * This property should be removed for supporting UHS mode
+ */
no-1-8-v;
- xlnx,mio_bank = <1>;
+ xlnx,mio-bank = <1>;
};
&serdes {