/*
* dts file for Xilinx ZynqMP ZCU104
*
- * (C) Copyright 2017 - 2018, Xilinx, Inc.
+ * (C) Copyright 2017 - 2020, Xilinx, Inc.
*
* Michal Simek <michal.simek@xilinx.com>
*/
#address-cells = <1>;
#size-cells = <0>;
reg = <2>;
- irps5401_43: irps54012@43 { /* IRPS5401 - u175 */
- #clock-cells = <0>;
+ irps5401_43: irps5401@43 { /* IRPS5401 - u175 */
compatible = "infineon,irps5401";
- reg = <0x43>;
+ reg = <0x43>; /* pmbus / i2c 0x13 */
};
- irps5401_4d: irps54012@4d { /* IRPS5401 - u180 */
- #clock-cells = <0>;
+ irps5401_44: irps5401@44 { /* IRPS5401 - u180 */
compatible = "infineon,irps5401";
- reg = <0x4d>;
+ reg = <0x44>; /* pmbus / i2c 0x14 */
};
};
spi-tx-bus-width = <1>;
spi-rx-bus-width = <4>;
spi-max-frequency = <108000000>; /* Based on DC1 spec */
- partition@qspi-fsbl-uboot { /* for testing purpose */
+ partition@0 { /* for testing purpose */
label = "qspi-fsbl-uboot";
reg = <0x0 0x100000>;
};
- partition@qspi-linux { /* for testing purpose */
+ partition@100000 { /* for testing purpose */
label = "qspi-linux";
reg = <0x100000 0x500000>;
};
- partition@qspi-device-tree { /* for testing purpose */
+ partition@600000 { /* for testing purpose */
label = "qspi-device-tree";
reg = <0x600000 0x20000>;
};
- partition@qspi-rootfs { /* for testing purpose */
+ partition@620000 { /* for testing purpose */
label = "qspi-rootfs";
reg = <0x620000 0x5E0000>;
};