Merge branch 'master' of git://git.denx.de/u-boot-spi

[platform/kernel/u-boot.git] / arch / arm / dts / zynqmp-zc1751-xm015-dc1.dts

diff --git a/arch/arm/dts/zynqmp-zc1751-xm015-dc1.dts b/arch/arm/dts/zynqmp-zc1751-xm015-dc1.dts
index c68a41b..9768dfe 100644 (file)
--- a/arch/arm/dts/zynqmp-zc1751-xm015-dc1.dts
+++ b/arch/arm/dts/zynqmp-zc1751-xm015-dc1.dts
@@ -1,17 +1,16 @@
+// SPDX-License-Identifier: GPL-2.0+
 /*
  * dts file for Xilinx ZynqMP zc1751-xm015-dc1
  *
- * (C) Copyright 2015, Xilinx, Inc.
+ * (C) Copyright 2015 - 2018, Xilinx, Inc.
  *
  * Michal Simek <michal.simek@xilinx.com>
- *
- * SPDX-License-Identifier:    GPL-2.0+
  */
 
 /dts-v1/;
 
 #include "zynqmp.dtsi"
-#include "zynqmp-clk.dtsi"
+#include "zynqmp-clk-ccf.dtsi"
 
 / {
        model = "ZynqMP zc1751-xm015-dc1 RevA";
@@ -34,25 +33,18 @@
                stdout-path = "serial0:115200n8";
        };
 
-       memory {
+       memory@0 {
                device_type = "memory";
                reg = <0x0 0x0 0x0 0x80000000>, <0x8 0x00000000 0x0 0x80000000>;
        };
 };
 
-/* fpd_dma clk 667MHz, lpd_dma 500MHz */
 &fpd_dma_chan1 {
        status = "okay";
-       xlnx,include-sg; /* for testing purpose */
-       xlnx,overfetch; /* for testing purpose */
-       xlnx,ratectrl = <0>; /* for testing purpose */
-       xlnx,src-issue = <31>;
 };
 
 &fpd_dma_chan2 {
        status = "okay";
-       xlnx,ratectrl = <100>; /* for testing purpose */
-       xlnx,src-issue = <4>; /* for testing purpose */
 };
 
 &fpd_dma_chan3 {
@@ -61,7 +53,6 @@
 
 &fpd_dma_chan4 {
        status = "okay";
-       xlnx,include-sg; /* for testing purpose */
 };
 
 &fpd_dma_chan5 {
@@ -70,7 +61,6 @@
 
 &fpd_dma_chan6 {
        status = "okay";
-       xlnx,include-sg; /* for testing purpose */
 };
 
 &fpd_dma_chan7 {
@@ -79,12 +69,10 @@
 
 &fpd_dma_chan8 {
        status = "okay";
-       xlnx,include-sg; /* for testing purpose */
 };
 
 &gem3 {
        status = "okay";
-       local-mac-address = [00 0a 35 00 02 90];
        phy-handle = <&phy0>;
        phy-mode = "rgmii-id";
        phy0: phy@0 {
@@ -103,8 +91,9 @@
 &i2c1 {
        status = "okay";
        clock-frequency = <400000>;
-       eeprom@55 {
-               compatible = "at,24c64"; /* 24AA64 */
+
+       eeprom: eeprom@55 {
+               compatible = "atmel,24c64"; /* 24AA64 */
                reg = <0x55>;
        };
 };
@@ -112,7 +101,7 @@
 &qspi {
        status = "okay";
        flash@0 {
-               compatible = "m25p80"; /* Micron MT25QU512ABB8ESF */
+               compatible = "m25p80", "spi-flash"; /* Micron MT25QU512ABB8ESF */
                #address-cells = <1>;
                #size-cells = <1>;
                reg = <0x0>;
@@ -159,12 +148,14 @@
 &sdhci0 {
        status = "okay";
        bus-width = <8>;
+       xlnx,mio_bank = <0>;
 };
 
 /* SD1 with level shifter */
 &sdhci1 {
        status = "okay";
        no-1-8-v;       /* for 1.0 silicon */
+       xlnx,mio_bank = <1>;
 };
 
 &uart0 {
@@ -174,6 +165,10 @@
 /* ULPI SMSC USB3320 */
 &usb0 {
        status = "okay";
+};
+
+&dwc3_0 {
+       status = "okay";
        dr_mode = "host";
 };