+// SPDX-License-Identifier: GPL-2.0+
/*
* dts file for Xilinx ZynqMP zc1751-xm015-dc1
*
- * (C) Copyright 2015, Xilinx, Inc.
+ * (C) Copyright 2015 - 2018, Xilinx, Inc.
*
* Michal Simek <michal.simek@xilinx.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
*/
/dts-v1/;
#include "zynqmp.dtsi"
-#include "zynqmp-clk.dtsi"
+#include "zynqmp-clk-ccf.dtsi"
/ {
model = "ZynqMP zc1751-xm015-dc1 RevA";
};
};
-/* fpd_dma clk 667MHz, lpd_dma 500MHz */
&fpd_dma_chan1 {
status = "okay";
- xlnx,include-sg; /* for testing purpose */
- xlnx,overfetch; /* for testing purpose */
- xlnx,ratectrl = <0>; /* for testing purpose */
- xlnx,src-issue = <31>;
};
&fpd_dma_chan2 {
status = "okay";
- xlnx,ratectrl = <100>; /* for testing purpose */
- xlnx,src-issue = <4>; /* for testing purpose */
};
&fpd_dma_chan3 {
&fpd_dma_chan4 {
status = "okay";
- xlnx,include-sg; /* for testing purpose */
};
&fpd_dma_chan5 {
&fpd_dma_chan6 {
status = "okay";
- xlnx,include-sg; /* for testing purpose */
};
&fpd_dma_chan7 {
&fpd_dma_chan8 {
status = "okay";
- xlnx,include-sg; /* for testing purpose */
};
&gem3 {
status = "okay";
- local-mac-address = [00 0a 35 00 02 90];
phy-handle = <&phy0>;
phy-mode = "rgmii-id";
phy0: phy@0 {
&i2c1 {
status = "okay";
clock-frequency = <400000>;
- eeprom@55 {
- compatible = "at,24c64"; /* 24AA64 */
+
+ eeprom: eeprom@55 {
+ compatible = "atmel,24c64"; /* 24AA64 */
reg = <0x55>;
};
};
&qspi {
status = "okay";
flash@0 {
- compatible = "m25p80"; /* Micron MT25QU512ABB8ESF */
+ compatible = "m25p80", "spi-flash"; /* Micron MT25QU512ABB8ESF */
#address-cells = <1>;
#size-cells = <1>;
reg = <0x0>;