ARM: dts: sun8i: V3/V3s/S3: Sync from Linux v5.18-rc1

[platform/kernel/u-boot.git] / arch / arm / dts / sun8i-v3s.dtsi

diff --git a/arch/arm/dts/sun8i-v3s.dtsi b/arch/arm/dts/sun8i-v3s.dtsi
index 0c73416..084323d 100644 (file)
--- a/arch/arm/dts/sun8i-v3s.dtsi
+++ b/arch/arm/dts/sun8i-v3s.dtsi
@@ -1,5 +1,6 @@
 /*
  * Copyright (C) 2016 Icenowy Zheng <icenowy@aosc.xyz>
+ * Copyright (C) 2021 Tobias Schramm <t.schramm@manjaro.org>
  *
  * This file is dual-licensed: you can use it either under the terms
  * of the GPL or the X11 license, at your option. Note that this dual
@@ -157,12 +158,30 @@
                syscon: system-control@1c00000 {
                        compatible = "allwinner,sun8i-v3s-system-control",
                                     "allwinner,sun8i-h3-system-control";
-                       reg = <0x01c00000 0x1000>;
+                       reg = <0x01c00000 0xd0>;
                        #address-cells = <1>;
                        #size-cells = <1>;
                        ranges;
                };
 
+               nmi_intc: interrupt-controller@1c000d0 {
+                       compatible = "allwinner,sun8i-v3s-nmi",
+                                    "allwinner,sun9i-a80-nmi";
+                       interrupt-controller;
+                       #interrupt-cells = <2>;
+                       reg = <0x01c000d0 0x0c>;
+                       interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
+               };
+
+               dma: dma-controller@1c02000 {
+                       compatible = "allwinner,sun8i-v3s-dma";
+                       reg = <0x01c02000 0x1000>;
+                       interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
+                       clocks = <&ccu CLK_BUS_DMA>;
+                       resets = <&ccu RST_BUS_DMA>;
+                       #dma-cells = <1>;
+               };
+
                tcon0: lcd-controller@1c0c000 {
                        compatible = "allwinner,sun8i-v3s-tcon";
                        reg = <0x01c0c000 0x1000>;
@@ -266,6 +285,8 @@
                        interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
                        clocks = <&ccu CLK_BUS_CE>, <&ccu CLK_CE>;
                        clock-names = "ahb", "mod";
+                       dmas = <&dma 16>, <&dma 16>;
+                       dma-names = "rx", "tx";
                        resets = <&ccu RST_BUS_CE>;
                        reset-names = "ahb";
                };
@@ -329,6 +350,12 @@
                        #interrupt-cells = <3>;
 
                        /omit-if-no-ref/
+                       csi0_mclk_pin: csi0-mclk-pin {
+                               pins = "PE20";
+                               function = "csi_mipi";
+                       };
+
+                       /omit-if-no-ref/
                        csi1_8bit_pins: csi1-8bit-pins {
                                pins = "PE0", "PE2", "PE3", "PE8", "PE9",
                                       "PE10", "PE11", "PE12", "PE13", "PE14",
@@ -348,6 +375,12 @@
                        };
 
                        /omit-if-no-ref/
+                       i2c1_pb_pins: i2c1-pb-pins {
+                               pins = "PB8", "PB9";
+                               function = "i2c1";
+                       };
+
+                       /omit-if-no-ref/
                        i2c1_pe_pins: i2c1-pe-pins {
                                pins = "PE21", "PE22";
                                function = "i2c1";
@@ -401,6 +434,15 @@
                        clocks = <&osc24M>;
                };
 
+               pwm: pwm@1c21400 {
+                       compatible = "allwinner,sun8i-v3s-pwm",
+                                    "allwinner,sun7i-a20-pwm";
+                       reg = <0x01c21400 0xc>;
+                       clocks = <&osc24M>;
+                       #pwm-cells = <3>;
+                       status = "disabled";
+               };
+
                lradc: lradc@1c22800 {
                        compatible = "allwinner,sun4i-a10-lradc-keys";
                        reg = <0x01c22800 0x400>;
@@ -408,6 +450,25 @@
                        status = "disabled";
                };
 
+               codec: codec@1c22c00 {
+                       #sound-dai-cells = <0>;
+                       compatible = "allwinner,sun8i-v3s-codec";
+                       reg = <0x01c22c00 0x400>;
+                       interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
+                       clocks = <&ccu CLK_BUS_CODEC>, <&ccu CLK_AC_DIG>;
+                       clock-names = "apb", "codec";
+                       resets = <&ccu RST_BUS_CODEC>;
+                       dmas = <&dma 15>, <&dma 15>;
+                       dma-names = "rx", "tx";
+                       allwinner,codec-analog-controls = <&codec_analog>;
+                       status = "disabled";
+               };
+
+               codec_analog: codec-analog@1c23000 {
+                       compatible = "allwinner,sun8i-v3s-codec-analog";
+                       reg = <0x01c23000 0x4>;
+               };
+
                uart0: serial@1c28000 {
                        compatible = "snps,dw-apb-uart";
                        reg = <0x01c28000 0x400>;
@@ -415,6 +476,8 @@
                        reg-shift = <2>;
                        reg-io-width = <4>;
                        clocks = <&ccu CLK_BUS_UART0>;
+                       dmas = <&dma 6>, <&dma 6>;
+                       dma-names = "rx", "tx";
                        resets = <&ccu RST_BUS_UART0>;
                        status = "disabled";
                };
@@ -426,6 +489,8 @@
                        reg-shift = <2>;
                        reg-io-width = <4>;
                        clocks = <&ccu CLK_BUS_UART1>;
+                       dmas = <&dma 7>, <&dma 7>;
+                       dma-names = "rx", "tx";
                        resets = <&ccu RST_BUS_UART1>;
                        status = "disabled";
                };
@@ -437,6 +502,8 @@
                        reg-shift = <2>;
                        reg-io-width = <4>;
                        clocks = <&ccu CLK_BUS_UART2>;
+                       dmas = <&dma 8>, <&dma 8>;
+                       dma-names = "rx", "tx";
                        resets = <&ccu RST_BUS_UART2>;
                        pinctrl-0 = <&uart2_pins>;
                        pinctrl-names = "default";
@@ -516,6 +583,8 @@
                        interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
                        clocks = <&ccu CLK_BUS_SPI0>, <&ccu CLK_SPI0>;
                        clock-names = "ahb", "mod";
+                       dmas = <&dma 23>, <&dma 23>;
+                       dma-names = "rx", "tx";
                        pinctrl-names = "default";
                        pinctrl-0 = <&spi0_pins>;
                        resets = <&ccu RST_BUS_SPI0>;
@@ -524,6 +593,17 @@
                        #size-cells = <0>;
                };
 
+               gic: interrupt-controller@1c81000 {
+                       compatible = "arm,gic-400";
+                       reg = <0x01c81000 0x1000>,
+                             <0x01c82000 0x2000>,
+                             <0x01c84000 0x2000>,
+                             <0x01c86000 0x2000>;
+                       interrupt-controller;
+                       #interrupt-cells = <3>;
+                       interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
+               };
+
                csi1: camera@1cb4000 {
                        compatible = "allwinner,sun8i-v3s-csi";
                        reg = <0x01cb4000 0x3000>;
@@ -535,16 +615,5 @@
                        resets = <&ccu RST_BUS_CSI>;
                        status = "disabled";
                };
-
-               gic: interrupt-controller@1c81000 {
-                       compatible = "arm,gic-400";
-                       reg = <0x01c81000 0x1000>,
-                             <0x01c82000 0x1000>,
-                             <0x01c84000 0x2000>,
-                             <0x01c86000 0x2000>;
-                       interrupt-controller;
-                       #interrupt-cells = <3>;
-                       interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
-               };
        };
 };