ARM: dts: stm32: Add DFU support for DHCOR recovery

[platform/kernel/u-boot.git] / arch / arm / dts / stm32mp15xx-dhcor-u-boot.dtsi

diff --git a/arch/arm/dts/stm32mp15xx-dhcor-u-boot.dtsi b/arch/arm/dts/stm32mp15xx-dhcor-u-boot.dtsi
index ef730a8..7137551 100644 (file)
--- a/arch/arm/dts/stm32mp15xx-dhcor-u-boot.dtsi
+++ b/arch/arm/dts/stm32mp15xx-dhcor-u-boot.dtsi
@@ -21,8 +21,13 @@
        };
 };
 
+&flash0 {
+       u-boot,dm-spl;
+};
+
 &i2c4 {
        u-boot,dm-pre-reloc;
+       u-boot,dm-spl;
 };
 
 &i2c4_pins_a {
@@ -34,12 +39,38 @@
 
 &pmic {
        u-boot,dm-pre-reloc;
+       u-boot,dm-spl;
+
+       regulators {
+               u-boot,dm-spl;
+       };
+};
+
+&pwr_regulators {
+       u-boot,dm-spl;
 };
 
 &qspi {
        u-boot,dm-spl;
 };
 
+&qspi_clk_pins_a {
+       u-boot,dm-spl;
+       pins {
+               u-boot,dm-spl;
+       };
+};
+
+&qspi_bk1_pins_a {
+       u-boot,dm-spl;
+       pins1 {
+               u-boot,dm-spl;
+       };
+       pins2 {
+               u-boot,dm-spl;
+       };
+};
+
 &rcc {
        st,clksrc = <
                CLK_MPU_PLL1P
@@ -105,15 +136,6 @@
                CLK_LPTIM45_LSE
        >;
 
-       /* VCO = 1300.0 MHz => P = 650 (CPU) */
-       pll1: st,pll@0 {
-               compatible = "st,stm32mp1-pll";
-               reg = <0>;
-               cfg = < 2 80 0 0 0 PQR(1,0,0) >;
-               frac = < 0x800 >;
-               u-boot,dm-pre-reloc;
-       };
-
        /* VCO = 1066.0 MHz => P = 266 (AXI), Q = 533 (GPU), R = 533 (DDR) */
        pll2: st,pll@1 {
                compatible = "st,stm32mp1-pll";
@@ -132,11 +154,43 @@
                u-boot,dm-pre-reloc;
        };
 
-       /* VCO = 600.0 MHz => P = 100, Q = 50, R = 100 */
+       /* VCO = 600.0 MHz => P = 99, Q = 74, R = 99 */
        pll4: st,pll@3 {
                compatible = "st,stm32mp1-pll";
                reg = <3>;
-               cfg = < 1 49 5 11 5 PQR(1,1,1) >;
+               cfg = < 3 98 5 7 5 PQR(1,1,1) >;
                u-boot,dm-pre-reloc;
        };
 };
+
+&reg11 {
+       u-boot,dm-spl;
+};
+
+&reg18 {
+       u-boot,dm-spl;
+};
+
+&usbotg_hs {
+       u-boot,dm-spl;
+};
+
+&usbphyc {
+       u-boot,dm-spl;
+};
+
+&usbphyc_port0 {
+       u-boot,dm-spl;
+};
+
+&usbphyc_port1 {
+       u-boot,dm-spl;
+};
+
+&vdd_io {
+       u-boot,dm-spl;
+};
+
+&vdd_usb {
+       u-boot,dm-spl;
+};