Merge tag 'u-boot-atmel-fixes-2021.01-b' of https://gitlab.denx.de/u-boot/custodians...
[platform/kernel/u-boot.git] / arch / arm / dts / stm32mp15-u-boot.dtsi
index 8f9535a..d0aa5ea 100644 (file)
 
        reboot {
                u-boot,dm-pre-reloc;
+               compatible = "syscon-reboot";
+               regmap = <&rcc>;
+               offset = <0x404>;
+               mask = <0x1>;
        };
 
        soc {
                u-boot,dm-pre-reloc;
+
+               ddr: ddr@5a003000 {
+                       u-boot,dm-pre-reloc;
+
+                       compatible = "st,stm32mp1-ddr";
+
+                       reg = <0x5A003000 0x550
+                              0x5A004000 0x234>;
+
+                       clocks = <&rcc AXIDCG>,
+                                <&rcc DDRC1>,
+                                <&rcc DDRC2>,
+                                <&rcc DDRPHYC>,
+                                <&rcc DDRCAPB>,
+                                <&rcc DDRPHYCAPB>;
+
+                       clock-names = "axidcg",
+                                     "ddrc1",
+                                     "ddrc2",
+                                     "ddrphyc",
+                                     "ddrcapb",
+                                     "ddrphycapb";
+
+                       status = "okay";
+               };
        };
 };
 
 &bsec {
-       u-boot,dm-pre-proper;
+       u-boot,dm-pre-reloc;
 };
 
 &clk_csi {
        u-boot,dm-pre-reloc;
 };
 
+&cpu0_opp_table {
+       u-boot,dm-spl;
+       opp-650000000 {
+               u-boot,dm-spl;
+       };
+       opp-800000000 {
+               u-boot,dm-spl;
+       };
+};
+
 &gpioa {
        u-boot,dm-pre-reloc;
 };
        u-boot,dm-pre-proper;
 };
 
+/* temp = waiting kernel update */
+&m4_rproc {
+       resets = <&rcc MCU_R>,
+                <&rcc MCU_HOLD_BOOT_R>;
+       reset-names = "mcu_rst", "hold_boot";
+};
+
 &pinctrl {
        u-boot,dm-pre-reloc;
 };
        compatible = "st,stm32-sdmmc2", "arm,pl18x", "arm,primecell";
 };
 
+&usart1 {
+       resets = <&rcc USART1_R>;
+};
+
+&usart2 {
+       resets = <&rcc USART2_R>;
+};
+
+&usart3 {
+       resets = <&rcc USART3_R>;
+};
+
+&uart4 {
+       resets = <&rcc UART4_R>;
+};
+
+&uart5 {
+       resets = <&rcc UART5_R>;
+};
+
+&usart6 {
+       resets = <&rcc USART6_R>;
+};
+
+&uart7 {
+       resets = <&rcc UART7_R>;
+};
+
+&uart8{
+       resets = <&rcc UART8_R>;
+};
+
 &usbotg_hs {
        compatible = "st,stm32mp1-hsotg", "snps,dwc2";
 };