* OTHER DEALINGS IN THE SOFTWARE.
*/
-#include <dt-bindings/pinctrl/stm32h7-pinfunc.h>
+#include <dt-bindings/pinctrl/stm32-pinfunc.h>
/ {
soc {
- pin-controller {
+ pinctrl: pin-controller {
#address-cells = <1>;
#size-cells = <1>;
compatible = "st,stm32h743-pinctrl";
ranges = <0 0x58020000 0x3000>;
+ interrupt-parent = <&exti>;
+ st,syscfg = <&syscfg 0x8>;
pins-are-numbered;
gpioa: gpio@58020000 {
gpio-controller;
#gpio-cells = <2>;
- compatible = "st,stm32-gpio";
reg = <0x0 0x400>;
clocks = <&rcc GPIOA_CK>;
st,bank-name = "GPIOA";
+ interrupt-controller;
+ #interrupt-cells = <2>;
};
gpiob: gpio@58020400 {
gpio-controller;
#gpio-cells = <2>;
- compatible = "st,stm32-gpio";
reg = <0x400 0x400>;
clocks = <&rcc GPIOB_CK>;
st,bank-name = "GPIOB";
+ interrupt-controller;
+ #interrupt-cells = <2>;
};
gpioc: gpio@58020800 {
gpio-controller;
#gpio-cells = <2>;
- compatible = "st,stm32-gpio";
reg = <0x800 0x400>;
clocks = <&rcc GPIOC_CK>;
st,bank-name = "GPIOC";
+ interrupt-controller;
+ #interrupt-cells = <2>;
};
gpiod: gpio@58020c00 {
gpio-controller;
#gpio-cells = <2>;
- compatible = "st,stm32-gpio";
reg = <0xc00 0x400>;
clocks = <&rcc GPIOD_CK>;
st,bank-name = "GPIOD";
+ interrupt-controller;
+ #interrupt-cells = <2>;
};
gpioe: gpio@58021000 {
gpio-controller;
#gpio-cells = <2>;
- compatible = "st,stm32-gpio";
reg = <0x1000 0x400>;
clocks = <&rcc GPIOE_CK>;
st,bank-name = "GPIOE";
+ interrupt-controller;
+ #interrupt-cells = <2>;
};
gpiof: gpio@58021400 {
gpio-controller;
#gpio-cells = <2>;
- compatible = "st,stm32-gpio";
reg = <0x1400 0x400>;
clocks = <&rcc GPIOF_CK>;
st,bank-name = "GPIOF";
+ interrupt-controller;
+ #interrupt-cells = <2>;
};
gpiog: gpio@58021800 {
gpio-controller;
#gpio-cells = <2>;
- compatible = "st,stm32-gpio";
reg = <0x1800 0x400>;
clocks = <&rcc GPIOG_CK>;
st,bank-name = "GPIOG";
+ interrupt-controller;
+ #interrupt-cells = <2>;
};
gpioh: gpio@58021c00 {
gpio-controller;
#gpio-cells = <2>;
- compatible = "st,stm32-gpio";
reg = <0x1c00 0x400>;
clocks = <&rcc GPIOH_CK>;
st,bank-name = "GPIOH";
+ interrupt-controller;
+ #interrupt-cells = <2>;
};
gpioi: gpio@58022000 {
gpio-controller;
#gpio-cells = <2>;
- compatible = "st,stm32-gpio";
reg = <0x2000 0x400>;
clocks = <&rcc GPIOI_CK>;
st,bank-name = "GPIOI";
+ interrupt-controller;
+ #interrupt-cells = <2>;
};
gpioj: gpio@58022400 {
gpio-controller;
#gpio-cells = <2>;
- compatible = "st,stm32-gpio";
reg = <0x2400 0x400>;
clocks = <&rcc GPIOJ_CK>;
st,bank-name = "GPIOJ";
+ interrupt-controller;
+ #interrupt-cells = <2>;
};
gpiok: gpio@58022800 {
gpio-controller;
#gpio-cells = <2>;
- compatible = "st,stm32-gpio";
reg = <0x2800 0x400>;
clocks = <&rcc GPIOK_CK>;
st,bank-name = "GPIOK";
+ interrupt-controller;
+ #interrupt-cells = <2>;
};
- usart1_pins: usart1@0 {
- pins1 {
- pinmux = <STM32H7_PB14_FUNC_USART1_TX>;
+ i2c1_pins_a: i2c1-0 {
+ pins {
+ pinmux = <STM32_PINMUX('B', 6, AF4)>, /* I2C1_SCL */
+ <STM32_PINMUX('B', 7, AF4)>; /* I2C1_SDA */
bias-disable;
- drive-push-pull;
+ drive-open-drain;
slew-rate = <0>;
};
- pins2 {
- pinmux = <STM32H7_PB15_FUNC_USART1_RX>;
+ };
+
+ ethernet_rmii: rmii-0 {
+ pins {
+ pinmux = <STM32_PINMUX('G', 11, AF11)>,
+ <STM32_PINMUX('G', 13, AF11)>,
+ <STM32_PINMUX('G', 12, AF11)>,
+ <STM32_PINMUX('C', 4, AF11)>,
+ <STM32_PINMUX('C', 5, AF11)>,
+ <STM32_PINMUX('A', 7, AF11)>,
+ <STM32_PINMUX('C', 1, AF11)>,
+ <STM32_PINMUX('A', 2, AF11)>,
+ <STM32_PINMUX('A', 1, AF11)>;
+ slew-rate = <2>;
+ };
+ };
+
+ sdmmc1_b4_pins_a: sdmmc1-b4-0 {
+ pins {
+ pinmux = <STM32_PINMUX('C', 8, AF12)>, /* SDMMC1_D0 */
+ <STM32_PINMUX('C', 9, AF12)>, /* SDMMC1_D1 */
+ <STM32_PINMUX('C', 10, AF12)>, /* SDMMC1_D2 */
+ <STM32_PINMUX('C', 11, AF12)>, /* SDMMC1_D3 */
+ <STM32_PINMUX('C', 12, AF12)>, /* SDMMC1_CK */
+ <STM32_PINMUX('D', 2, AF12)>; /* SDMMC1_CMD */
+ slew-rate = <3>;
+ drive-push-pull;
bias-disable;
};
};
- usart2_pins: usart2@0 {
+ sdmmc1_b4_od_pins_a: sdmmc1-b4-od-0 {
pins1 {
- pinmux = <STM32H7_PD5_FUNC_USART2_TX>;
- bias-disable;
+ pinmux = <STM32_PINMUX('C', 8, AF12)>, /* SDMMC1_D0 */
+ <STM32_PINMUX('C', 9, AF12)>, /* SDMMC1_D1 */
+ <STM32_PINMUX('C', 10, AF12)>, /* SDMMC1_D2 */
+ <STM32_PINMUX('C', 11, AF12)>, /* SDMMC1_D3 */
+ <STM32_PINMUX('C', 12, AF12)>; /* SDMMC1_CK */
+ slew-rate = <3>;
drive-push-pull;
- slew-rate = <0>;
+ bias-disable;
};
- pins2 {
- pinmux = <STM32H7_PD6_FUNC_USART2_RX>;
+ pins2{
+ pinmux = <STM32_PINMUX('D', 2, AF12)>; /* SDMMC1_CMD */
+ slew-rate = <3>;
+ drive-open-drain;
bias-disable;
};
};
- fmc_pins: fmc@0 {
- pins {
- pinmux = <STM32H7_PD0_FUNC_FMC_D2_FMC_DA2>,
- <STM32H7_PD1_FUNC_FMC_D3_FMC_DA3>,
- <STM32H7_PD8_FUNC_FMC_D13_FMC_DA13>,
- <STM32H7_PD9_FUNC_FMC_D14_FMC_DA14>,
- <STM32H7_PD10_FUNC_FMC_D15_FMC_DA15>,
- <STM32H7_PD14_FUNC_FMC_D0_FMC_DA0>,
- <STM32H7_PD15_FUNC_FMC_D1_FMC_DA1>,
-
- <STM32H7_PE0_FUNC_FMC_NBL0>,
- <STM32H7_PE1_FUNC_FMC_NBL1>,
- <STM32H7_PE7_FUNC_FMC_D4_FMC_DA4>,
- <STM32H7_PE8_FUNC_FMC_D5_FMC_DA5>,
- <STM32H7_PE9_FUNC_FMC_D6_FMC_DA6>,
- <STM32H7_PE10_FUNC_FMC_D7_FMC_DA7>,
- <STM32H7_PE11_FUNC_FMC_D8_FMC_DA8>,
- <STM32H7_PE12_FUNC_FMC_D9_FMC_DA9>,
- <STM32H7_PE13_FUNC_FMC_D10_FMC_DA10>,
- <STM32H7_PE14_FUNC_FMC_D11_FMC_DA11>,
- <STM32H7_PE15_FUNC_FMC_D12_FMC_DA12>,
-
- <STM32H7_PF0_FUNC_FMC_A0>,
- <STM32H7_PF1_FUNC_FMC_A1>,
- <STM32H7_PF2_FUNC_FMC_A2>,
- <STM32H7_PF3_FUNC_FMC_A3>,
- <STM32H7_PF4_FUNC_FMC_A4>,
- <STM32H7_PF5_FUNC_FMC_A5>,
- <STM32H7_PF11_FUNC_FMC_SDNRAS>,
- <STM32H7_PF12_FUNC_FMC_A6>,
- <STM32H7_PF13_FUNC_FMC_A7>,
- <STM32H7_PF14_FUNC_FMC_A8>,
- <STM32H7_PF15_FUNC_FMC_A9>,
-
- <STM32H7_PG0_FUNC_FMC_A10>,
- <STM32H7_PG1_FUNC_FMC_A11>,
- <STM32H7_PG2_FUNC_FMC_A12>,
- <STM32H7_PG4_FUNC_FMC_A14_FMC_BA0>,
- <STM32H7_PG5_FUNC_FMC_A15_FMC_BA1>,
- <STM32H7_PG8_FUNC_FMC_SDCLK>,
- <STM32H7_PG15_FUNC_FMC_SDNCAS>,
-
- <STM32H7_PH5_FUNC_FMC_SDNWE>,
- <STM32H7_PH6_FUNC_FMC_SDNE1>,
- <STM32H7_PH7_FUNC_FMC_SDCKE1>,
- <STM32H7_PH8_FUNC_FMC_D16>,
- <STM32H7_PH9_FUNC_FMC_D17>,
- <STM32H7_PH10_FUNC_FMC_D18>,
- <STM32H7_PH11_FUNC_FMC_D19>,
- <STM32H7_PH12_FUNC_FMC_D20>,
- <STM32H7_PH13_FUNC_FMC_D21>,
- <STM32H7_PH14_FUNC_FMC_D22>,
- <STM32H7_PH15_FUNC_FMC_D23>,
-
- <STM32H7_PI0_FUNC_FMC_D24>,
- <STM32H7_PI1_FUNC_FMC_D25>,
- <STM32H7_PI2_FUNC_FMC_D26>,
- <STM32H7_PI3_FUNC_FMC_D27>,
- <STM32H7_PI4_FUNC_FMC_NBL2>,
- <STM32H7_PI5_FUNC_FMC_NBL3>,
- <STM32H7_PI6_FUNC_FMC_D28>,
- <STM32H7_PI7_FUNC_FMC_D29>,
- <STM32H7_PI9_FUNC_FMC_D30>,
- <STM32H7_PI10_FUNC_FMC_D31>;
+ sdmmc1_b4_sleep_pins_a: sdmmc1-b4-sleep-0 {
+ pins {
+ pinmux = <STM32_PINMUX('C', 8, ANALOG)>, /* SDMMC1_D0 */
+ <STM32_PINMUX('C', 9, ANALOG)>, /* SDMMC1_D1 */
+ <STM32_PINMUX('C', 10, ANALOG)>, /* SDMMC1_D2 */
+ <STM32_PINMUX('C', 11, ANALOG)>, /* SDMMC1_D3 */
+ <STM32_PINMUX('C', 12, ANALOG)>, /* SDMMC1_CK */
+ <STM32_PINMUX('D', 2, ANALOG)>; /* SDMMC1_CMD */
+ };
+ };
- slew-rate = <3>;
+ sdmmc1_dir_pins_a: sdmmc1-dir-0 {
+ pins1 {
+ pinmux = <STM32_PINMUX('C', 6, AF8)>, /* SDMMC1_D0DIR */
+ <STM32_PINMUX('C', 7, AF8)>, /* SDMMC1_D123DIR */
+ <STM32_PINMUX('B', 9, AF7)>; /* SDMMC1_CDIR */
+ slew-rate = <3>;
+ drive-push-pull;
+ bias-pull-up;
+ };
+ pins2{
+ pinmux = <STM32_PINMUX('B', 8, AF7)>; /* SDMMC1_CKIN */
+ bias-pull-up;
};
};
- sdmmc1_pins: sdmmc@0 {
+ sdmmc1_dir_sleep_pins_a: sdmmc1-dir-sleep-0 {
pins {
- pinmux = <STM32H7_PC8_FUNC_SDMMC1_D0>,
- <STM32H7_PC9_FUNC_SDMMC1_D1>,
- <STM32H7_PC10_FUNC_SDMMC1_D2>,
- <STM32H7_PC11_FUNC_SDMMC1_D3>,
- <STM32H7_PC12_FUNC_SDMMC1_CK>,
- <STM32H7_PD2_FUNC_SDMMC1_CMD>;
+ pinmux = <STM32_PINMUX('C', 6, ANALOG)>, /* SDMMC1_D0DIR */
+ <STM32_PINMUX('C', 7, ANALOG)>, /* SDMMC1_D123DIR */
+ <STM32_PINMUX('B', 9, ANALOG)>, /* SDMMC1_CDIR */
+ <STM32_PINMUX('B', 8, ANALOG)>; /* SDMMC1_CKIN */
+ };
+ };
- slew-rate = <3>;
+ usart1_pins: usart1-0 {
+ pins1 {
+ pinmux = <STM32_PINMUX('B', 14, AF4)>; /* USART1_TX */
+ bias-disable;
drive-push-pull;
+ slew-rate = <0>;
+ };
+ pins2 {
+ pinmux = <STM32_PINMUX('B', 15, AF4)>; /* USART1_RX */
bias-disable;
};
};
- pinctrl_sdmmc1_level_shifter: sdmmc0_ls@0 {
+ usart2_pins: usart2-0 {
+ pins1 {
+ pinmux = <STM32_PINMUX('D', 5, AF7)>; /* USART2_TX */
+ bias-disable;
+ drive-push-pull;
+ slew-rate = <0>;
+ };
+ pins2 {
+ pinmux = <STM32_PINMUX('D', 6, AF7)>; /* USART2_RX */
+ bias-disable;
+ };
+ };
+
+ usbotg_hs_pins_a: usbotg-hs-0 {
pins {
- pinmux = <STM32H7_PB8_FUNC_SDMMC1_CKIN>,
- <STM32H7_PB9_FUNC_SDMMC1_CDIR>,
- <STM32H7_PC6_FUNC_SDMMC1_D0DIR>,
- <STM32H7_PC7_FUNC_SDMMC1_D123DIR>;
+ pinmux = <STM32_PINMUX('H', 4, AF10)>, /* ULPI_NXT */
+ <STM32_PINMUX('I', 11, AF10)>, /* ULPI_DIR> */
+ <STM32_PINMUX('C', 0, AF10)>, /* ULPI_STP> */
+ <STM32_PINMUX('A', 5, AF10)>, /* ULPI_CK> */
+ <STM32_PINMUX('A', 3, AF10)>, /* ULPI_D0> */
+ <STM32_PINMUX('B', 0, AF10)>, /* ULPI_D1> */
+ <STM32_PINMUX('B', 1, AF10)>, /* ULPI_D2> */
+ <STM32_PINMUX('B', 10, AF10)>, /* ULPI_D3> */
+ <STM32_PINMUX('B', 11, AF10)>, /* ULPI_D4> */
+ <STM32_PINMUX('B', 12, AF10)>, /* ULPI_D5> */
+ <STM32_PINMUX('B', 13, AF10)>, /* ULPI_D6> */
+ <STM32_PINMUX('B', 5, AF10)>; /* ULPI_D7> */
+ bias-disable;
drive-push-pull;
- slew-rate = <3>;
+ slew-rate = <2>;
};
};
};
projects / platform / kernel / u-boot.git / blobdiff