+// SPDX-License-Identifier: GPL-2.0+ OR X11
/*
- * Copyright (C) 2017, STMicroelectronics - All Rights Reserved
- * Author(s): Alexandre Torgue <alexandre.torgue@st.com> for STMicroelectronics.
+ * Copyright 2017 - Alexandre Torgue <alexandre.torgue@st.com>
*
- * This file is dual-licensed: you can use it either under the terms
- * of the GPL or the X11 license, at your option. Note that this dual
- * licensing only applies to this file, and not this project as a
- * whole.
- *
- * a) This file is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of the
- * License, or (at your option) any later version.
- *
- * This file is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * Or, alternatively,
- *
- * b) Permission is hereby granted, free of charge, to any person
- * obtaining a copy of this software and associated documentation
- * files (the "Software"), to deal in the Software without
- * restriction, including without limitation the rights to use,
- * copy, modify, merge, publish, distribute, sublicense, and/or
- * sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following
- * conditions:
- *
- * The above copyright notice and this permission notice shall be
- * included in all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
- * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
- * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
- * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
*/
#include <dt-bindings/pinctrl/stm32-pinfunc.h>
st,bank-name = "GPIOK";
};
- usart1_pins_a: usart1@0 {
+ usart1_pins_a: usart1-0 {
pins1 {
pinmux = <STM32_PINMUX('A', 9, AF7)>; /* USART1_TX */
bias-disable;
};
};
- usart3_pins_a: usart3@0 {
+ usart3_pins_a: usart3-0 {
pins1 {
pinmux = <STM32_PINMUX('B', 10, AF7)>; /* USART3_TX */
bias-disable;
};
};
- usbotg_fs_pins_a: usbotg_fs@0 {
+ usbotg_fs_pins_a: usbotg-fs-0 {
pins {
pinmux = <STM32_PINMUX('A', 10, AF10)>, /* OTG_FS_ID */
<STM32_PINMUX('A', 11, AF10)>, /* OTG_FS_DM */
};
};
- usbotg_fs_pins_b: usbotg_fs@1 {
+ usbotg_fs_pins_b: usbotg-fs-1 {
pins {
pinmux = <STM32_PINMUX('B', 12, AF12)>, /* OTG_HS_ID */
<STM32_PINMUX('B', 14, AF12)>, /* OTG_HS_DM */
};
};
- usbotg_hs_pins_a: usbotg_hs@0 {
+ usbotg_hs_pins_a: usbotg-hs-0 {
pins {
pinmux = <STM32_PINMUX('H', 4, AF10)>, /* OTG_HS_ULPI_NXT*/
<STM32_PINMUX('I', 11, AF10)>, /* OTG_HS_ULPI_DIR */
};
};
- ethernet_mii: mii@0 {
+ ethernet_mii: mii-0 {
pins {
pinmux = <STM32_PINMUX('G', 13, AF11)>, /* ETH_MII_TXD0_ETH_RMII_TXD0 */
<STM32_PINMUX('G', 14, AF11)>, /* ETH_MII_TXD1_ETH_RMII_TXD1 */
};
};
- adc3_in8_pin: adc@200 {
+ adc3_in8_pin: adc-200 {
pins {
pinmux = <STM32_PINMUX('F', 10, ANALOG)>;
};
};
- pwm1_pins: pwm@1 {
+ pwm1_pins: pwm1-0 {
pins {
pinmux = <STM32_PINMUX('A', 8, AF1)>, /* TIM1_CH1 */
<STM32_PINMUX('B', 13, AF1)>, /* TIM1_CH1N */
};
};
- pwm3_pins: pwm@3 {
+ pwm3_pins: pwm3-0 {
pins {
pinmux = <STM32_PINMUX('B', 4, AF2)>, /* TIM3_CH1 */
<STM32_PINMUX('B', 5, AF2)>; /* TIM3_CH2 */
};
};
- i2c1_pins: i2c1@0 {
+ i2c1_pins: i2c1-0 {
pins {
pinmux = <STM32_PINMUX('B', 9, AF4)>, /* I2C1_SDA */
<STM32_PINMUX('B', 6, AF4)>; /* I2C1_SCL */
};
};
- ltdc_pins: ltdc@0 {
+ ltdc_pins_a: ltdc-0 {
pins {
pinmux = <STM32_PINMUX('I', 12, AF14)>, /* LCD_HSYNC */
<STM32_PINMUX('I', 13, AF14)>, /* LCD_VSYNC */
};
};
- dcmi_pins: dcmi@0 {
+ ltdc_pins_b: ltdc-1 {
+ pins {
+ pinmux = <STM32_PINMUX('C', 6, AF14)>,
+ /* LCD_HSYNC */
+ <STM32_PINMUX('A', 4, AF14)>,
+ /* LCD_VSYNC */
+ <STM32_PINMUX('G', 7, AF14)>,
+ /* LCD_CLK */
+ <STM32_PINMUX('C', 10, AF14)>,
+ /* LCD_R2 */
+ <STM32_PINMUX('B', 0, AF9)>,
+ /* LCD_R3 */
+ <STM32_PINMUX('A', 11, AF14)>,
+ /* LCD_R4 */
+ <STM32_PINMUX('A', 12, AF14)>,
+ /* LCD_R5 */
+ <STM32_PINMUX('B', 1, AF9)>,
+ /* LCD_R6*/
+ <STM32_PINMUX('G', 6, AF14)>,
+ /* LCD_R7 */
+ <STM32_PINMUX('A', 6, AF14)>,
+ /* LCD_G2 */
+ <STM32_PINMUX('G', 10, AF9)>,
+ /* LCD_G3 */
+ <STM32_PINMUX('B', 10, AF14)>,
+ /* LCD_G4 */
+ <STM32_PINMUX('D', 6, AF14)>,
+ /* LCD_B2 */
+ <STM32_PINMUX('G', 11, AF14)>,
+ /* LCD_B3*/
+ <STM32_PINMUX('B', 11, AF14)>,
+ /* LCD_G5 */
+ <STM32_PINMUX('C', 7, AF14)>,
+ /* LCD_G6 */
+ <STM32_PINMUX('D', 3, AF14)>,
+ /* LCD_G7 */
+ <STM32_PINMUX('G', 12, AF9)>,
+ /* LCD_B4 */
+ <STM32_PINMUX('A', 3, AF14)>,
+ /* LCD_B5 */
+ <STM32_PINMUX('B', 8, AF14)>,
+ /* LCD_B6 */
+ <STM32_PINMUX('B', 9, AF14)>,
+ /* LCD_B7 */
+ <STM32_PINMUX('F', 10, AF14)>;
+ /* LCD_DE */
+ slew-rate = <2>;
+ };
+ };
+
+ spi5_pins: spi5-0 {
+ pins1 {
+ pinmux = <STM32_PINMUX('F', 7, AF5)>,
+ /* SPI5_CLK */
+ <STM32_PINMUX('F', 9, AF5)>;
+ /* SPI5_MOSI */
+ bias-disable;
+ drive-push-pull;
+ slew-rate = <0>;
+ };
+ pins2 {
+ pinmux = <STM32_PINMUX('F', 8, AF5)>;
+ /* SPI5_MISO */
+ bias-disable;
+ };
+ };
+
+ i2c3_pins: i2c3-0 {
+ pins {
+ pinmux = <STM32_PINMUX('C', 9, AF4)>,
+ /* I2C3_SDA */
+ <STM32_PINMUX('A', 8, AF4)>;
+ /* I2C3_SCL */
+ bias-disable;
+ drive-open-drain;
+ slew-rate = <3>;
+ };
+ };
+
+ dcmi_pins: dcmi-0 {
pins {
pinmux = <STM32_PINMUX('A', 4, AF13)>, /* DCMI_HSYNC */
<STM32_PINMUX('B', 7, AF13)>, /* DCMI_VSYNC */
};
};
- sdio_pins: sdio_pins@0 {
+ sdio_pins: sdio-pins-0 {
pins {
- pinmux = <STM32_PINMUX('C', 8, AF12)>,
- <STM32_PINMUX('C', 9, AF12)>,
- <STM32_PINMUX('C', 10, AF12)>,
- <STM32_PINMUX('c', 11, AF12)>,
- <STM32_PINMUX('C', 12, AF12)>,
- <STM32_PINMUX('D', 2, AF12)>;
+ pinmux = <STM32_PINMUX('C', 8, AF12)>, /* SDIO_D0 */
+ <STM32_PINMUX('C', 9, AF12)>, /* SDIO_D1 */
+ <STM32_PINMUX('C', 10, AF12)>, /* SDIO_D2 */
+ <STM32_PINMUX('C', 11, AF12)>, /* SDIO_D3 */
+ <STM32_PINMUX('C', 12, AF12)>, /* SDIO_CK */
+ <STM32_PINMUX('D', 2, AF12)>; /* SDIO_CMD */
drive-push-pull;
slew-rate = <2>;
};
};
- sdio_pins_od: sdio_pins_od@0 {
+ sdio_pins_od: sdio-pins-od-0 {
pins1 {
- pinmux = <STM32_PINMUX('C', 8, AF12)>,
- <STM32_PINMUX('C', 9, AF12)>,
- <STM32_PINMUX('C', 10, AF12)>,
- <STM32_PINMUX('C', 11, AF12)>,
- <STM32_PINMUX('C', 12, AF12)>;
+ pinmux = <STM32_PINMUX('C', 8, AF12)>, /* SDIO_D0 */
+ <STM32_PINMUX('C', 9, AF12)>, /* SDIO_D1 */
+ <STM32_PINMUX('C', 10, AF12)>, /* SDIO_D2 */
+ <STM32_PINMUX('C', 11, AF12)>, /* SDIO_D3 */
+ <STM32_PINMUX('C', 12, AF12)>; /* SDIO_CK */
drive-push-pull;
slew-rate = <2>;
};
pins2 {
- pinmux = <STM32_PINMUX('D', 2, AF12)>;
+ pinmux = <STM32_PINMUX('D', 2, AF12)>; /* SDIO_CMD */
drive-open-drain;
slew-rate = <2>;
};
projects / platform / kernel / u-boot.git / blobdiff