Merge branch 'master' of git://git.denx.de/u-boot-spi

[platform/kernel/u-boot.git] / arch / arm / dts / rv1108.dtsi

diff --git a/arch/arm/dts/rv1108.dtsi b/arch/arm/dts/rv1108.dtsi
index 77ca24e..215d885 100644 (file)
--- a/arch/arm/dts/rv1108.dtsi
+++ b/arch/arm/dts/rv1108.dtsi
@@ -1,7 +1,6 @@
+// SPDX-License-Identifier: GPL-2.0+
 /*
  * (C) Copyright 2016 Rockchip Electronics Co., Ltd
- *
- * SPDX-License-Identifier:     GPL-2.0+
  */
 
 #include <dt-bindings/gpio/gpio.h>
@@ -122,8 +121,46 @@
        };
 
        grf: syscon@10300000 {
-               compatible = "rockchip,rv1108-grf", "syscon";
+               compatible = "rockchip,rv1108-grf", "syscon", "simple-mfd";
                reg = <0x10300000 0x1000>;
+               #address-cells = <1>;
+               #size-cells = <1>;
+
+               u2phy: usb2-phy@100 {
+                       compatible = "rockchip,rv1108-usb2phy";
+                       reg = <0x100 0x0c>;
+                       clocks = <&cru SCLK_USBPHY>;
+                       clock-names = "phyclk";
+                       #clock-cells = <0>;
+                       clock-output-names = "usbphy";
+                       rockchip,usbgrf = <&usbgrf>;
+                       status = "disabled";
+
+                       u2phy_otg: otg-port {
+                               interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
+                               interrupt-names = "otg-mux";
+                               #phy-cells = <0>;
+                               status = "disabled";
+                       };
+
+                       u2phy_host: host-port {
+                               interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
+                               interrupt-names = "linestate";
+                               #phy-cells = <0>;
+                               status = "disabled";
+                       };
+               };
+       };
+
+       saradc: saradc@1038c000 {
+               compatible = "rockchip,rv1108-saradc", "rockchip,rk3399-saradc";
+               reg = <0x1038c000 0x100>;
+               interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
+               #io-channel-cells = <1>;
+               clock-frequency = <1000000>;
+               clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>;
+               clock-names = "saradc", "apb_pclk";
+               status = "disabled";
        };
 
        pmugrf: syscon@20060000 {
@@ -131,6 +168,11 @@
                reg = <0x20060000 0x1000>;
        };
 
+       usbgrf: syscon@202a0000 {
+               compatible = "rockchip,rv1108-usbgrf", "syscon";
+               reg = <0x202a0000 0x1000>;
+       };
+
        cru: clock-controller@20200000 {
                compatible = "rockchip,rv1108-cru";
                reg = <0x20200000 0x1000>;
@@ -175,6 +217,37 @@
                status = "disabled";
        };
 
+       usb_host_ehci: usb@30140000 {
+               compatible = "generic-ehci";
+               reg = <0x30140000 0x20000>;
+               interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
+               status = "disabled";
+       };
+
+       usb_host_ohci: usb@30160000 {
+               compatible = "generic-ohci";
+               reg = <0x30160000 0x20000>;
+               interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
+               status = "disabled";
+       };
+
+       usb20_otg: usb@30180000 {
+               compatible = "rockchip,rv1108-usb", "rockchip,rk3066-usb",
+                            "snps,dwc2";
+               reg = <0x30180000 0x40000>;
+               interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
+               clocks = <&cru HCLK_OTG>;
+               clock-names = "otg";
+               dr_mode = "otg";
+               g-np-tx-fifo-size = <16>;
+               g-rx-fifo-size = <280>;
+               g-tx-fifo-size = <256 128 128 64 32 16>;
+               g-use-dma;
+               phys = <&u2phy_otg>;
+               phy-names = "usb2-phy";
+               status = "disabled";
+       };
+
        sfc: sfc@301c0000 {
                compatible = "rockchip,sfc";
                reg = <0x301c0000 0x200>;
@@ -393,6 +466,35 @@
                        };
                };
 
+               emmc {
+                       emmc_clk: emmc-clk {
+                               rockchip,pins = <2 RK_PB6 RK_FUNC_1 &pcfg_pull_none_drv_8ma>;
+                       };
+
+                       emmc_cmd: emmc-cmd {
+                               rockchip,pins = <2 RK_PB4 RK_FUNC_2 &pcfg_pull_up_drv_8ma>;
+                       };
+
+                       emmc_pwren: emmc-pwren {
+                               rockchip,pins = <2 RK_PC2 RK_FUNC_2 &pcfg_pull_none>;
+                       };
+
+                       emmc_bus1: emmc-bus1 {
+                               rockchip,pins = <2 RK_PA0 RK_FUNC_2 &pcfg_pull_up_drv_8ma>;
+                       };
+
+                       emmc_bus8: emmc-bus8 {
+                               rockchip,pins = <2 RK_PA0 RK_FUNC_2 &pcfg_pull_up_drv_8ma>,
+                                               <2 RK_PA1 RK_FUNC_2 &pcfg_pull_up_drv_8ma>,
+                                               <2 RK_PA2 RK_FUNC_2 &pcfg_pull_up_drv_8ma>,
+                                               <2 RK_PA3 RK_FUNC_2 &pcfg_pull_up_drv_8ma>,
+                                               <2 RK_PA4 RK_FUNC_2 &pcfg_pull_up_drv_8ma>,
+                                               <2 RK_PA5 RK_FUNC_2 &pcfg_pull_up_drv_8ma>,
+                                               <2 RK_PA6 RK_FUNC_2 &pcfg_pull_up_drv_8ma>,
+                                               <2 RK_PA7 RK_FUNC_2 &pcfg_pull_up_drv_8ma>;
+                       };
+               };
+
                sdmmc {
                        sdmmc_clk: sdmmc-clk {
                                rockchip,pins = <3 RK_PC4 RK_FUNC_1 &pcfg_pull_none_drv_4ma>;