Merge tag 'u-boot-rockchip-20200501' of https://gitlab.denx.de/u-boot/custodians...

[platform/kernel/u-boot.git] / arch / arm / dts / rk3399-nanopi4.dtsi

diff --git a/arch/arm/dts/rk3399-nanopi4.dtsi b/arch/arm/dts/rk3399-nanopi4.dtsi
index d325e11..c88018a 100644 (file)
--- a/arch/arm/dts/rk3399-nanopi4.dtsi
+++ b/arch/arm/dts/rk3399-nanopi4.dtsi
@@ -48,7 +48,7 @@
        };
 
        /* switched by pmic_sleep */
-       vcc1v8_s3: vcca1v8_s3: vcc1v8-s3 {
+       vcc1v8_s3: vcc1v8-s3 {
                compatible = "regulator-fixed";
                regulator-always-on;
                regulator-boot-on;
@@ -71,6 +71,27 @@
                vin-supply = <&vcc3v3_sys>;
        };
 
+       /*
+        * Really, this is supplied by vcc_1v8, and vcc1v8_s3 only
+        * drives the enable pin, but we can't quite model that.
+        */
+       vcca0v9_s3: vcca0v9-s3 {
+               compatible = "regulator-fixed";
+               regulator-min-microvolt = <900000>;
+               regulator-max-microvolt = <900000>;
+               regulator-name = "vcca0v9_s3";
+               vin-supply = <&vcc1v8_s3>;
+       };
+
+       /* As above, actually supplied by vcc3v3_sys */
+       vcca1v8_s3: vcca1v8-s3 {
+               compatible = "regulator-fixed";
+               regulator-min-microvolt = <1800000>;
+               regulator-max-microvolt = <1800000>;
+               regulator-name = "vcca1v8_s3";
+               vin-supply = <&vcc1v8_s3>;
+       };
+
        vbus_typec: vbus-typec {
                compatible = "regulator-fixed";
                regulator-min-microvolt = <5000000>;
@@ -148,15 +169,28 @@
        assigned-clocks = <&cru SCLK_RMII_SRC>;
        clock_in_out = "input";
        pinctrl-names = "default";
-       pinctrl-0 = <&rgmii_pins>;
+       pinctrl-0 = <&rgmii_pins>, <&phy_intb>, <&phy_rstb>;
+       phy-handle = <&rtl8211e>;
        phy-mode = "rgmii";
        phy-supply = <&vcc3v3_s3>;
-       snps,reset-active-low;
-       snps,reset-delays-us = <0 10000 50000>;
-       snps,reset-gpio = <&gpio3 RK_PB7 GPIO_ACTIVE_LOW>;
        tx_delay = <0x28>;
        rx_delay = <0x11>;
        status = "okay";
+
+       mdio {
+               compatible = "snps,dwmac-mdio";
+               #address-cells = <1>;
+               #size-cells = <0>;
+
+               rtl8211e: phy@1 {
+                       reg = <1>;
+                       interrupt-parent = <&gpio3>;
+                       interrupts = <RK_PB2 IRQ_TYPE_LEVEL_LOW>;
+                       reset-assert-us = <10000>;
+                       reset-deassert-us = <30000>;
+                       reset-gpios = <&gpio3 RK_PB7 GPIO_ACTIVE_LOW>;
+               };
+       };
 };
 
 &gpu {
@@ -171,6 +205,10 @@
        status = "okay";
 };
 
+&hdmi_sound {
+       status = "okay";
+};
+
 &i2c0 {
        clock-frequency = <400000>;
        i2c-scl-rising-time-ns = <160>;
@@ -446,6 +484,10 @@
        status = "okay";
 };
 
+&i2s2 {
+       status = "okay";
+};
+
 &io_domains {
        bt656-supply = <&vcc_1v8>;
        audio-supply = <&vcca1v8_codec>;
@@ -464,7 +506,9 @@
 &pcie0 {
        ep-gpios = <&gpio2 RK_PA4 GPIO_ACTIVE_HIGH>;
        max-link-speed = <2>;
-       num-lanes = <4>;
+       num-lanes = <2>;
+       vpcie0v9-supply = <&vcca0v9_s3>;
+       vpcie1v8-supply = <&vcca1v8_s3>;
        status = "okay";
 };
 
@@ -481,6 +525,16 @@
                };
        };
 
+       phy {
+               phy_intb: phy-intb {
+                       rockchip,pins = <3 RK_PB2 RK_FUNC_GPIO &pcfg_pull_up>;
+               };
+
+               phy_rstb: phy-rstb {
+                       rockchip,pins = <3 RK_PB7 RK_FUNC_GPIO &pcfg_pull_none>;
+               };
+       };
+
        pmic {
                cpu_b_sleep: cpu-b-sleep {
                        rockchip,pins = <1 RK_PC1 RK_FUNC_GPIO &pcfg_pull_down>;