Merge branch 'master' into next

[platform/kernel/u-boot.git] / arch / arm / dts / rk3188-radxarock-u-boot.dtsi

diff --git a/arch/arm/dts/rk3188-radxarock-u-boot.dtsi b/arch/arm/dts/rk3188-radxarock-u-boot.dtsi
index 013535a..7bcbc29 100644 (file)
--- a/arch/arm/dts/rk3188-radxarock-u-boot.dtsi
+++ b/arch/arm/dts/rk3188-radxarock-u-boot.dtsi
@@ -3,21 +3,59 @@
  * Copyright (c) 2018 Fuzhou Rockchip Electronics Co., Ltd.
  */
 
+#include "rk3188-u-boot.dtsi"
+
+/ {
+       chosen {
+/*             stdout-path = &uart2; */
+               stdout-path = "serial2:115200n8";
+       };
+
+       config {
+               u-boot,boot-led = "rock:red:power";
+               bootph-all;
+       };
+};
+
 &cru {
-       u-boot,dm-spl;
+       bootph-pre-ram;
 };
 
-&pinctrl {
-       u-boot,dm-spl;
+&dmc {
+       rockchip,pctl-timing = <0x12c 0xc8 0x1f4 0x1e 0x4e 0x4 0x69 0x6
+               0x3 0x0 0x6 0x5 0xc 0x10 0x6 0x4
+               0x4 0x5 0x4 0x200 0x3 0xa 0x40 0x0
+               0x1 0x5 0x5 0x3 0xc 0x1e 0x100 0x0
+               0x4 0x0>;
+       rockchip,phy-timing = <0x208c6690 0x690878 0x10022a00
+               0x220 0x40 0x0 0x0>;
+       rockchip,sdram-params = <0x24716310 0 2 300000000 3 9 0>;
 };
 
-&uart2 {
-       status = "okay";
-       u-boot,dm-spl;
+&emmc {
+       fifo-mode;
+       max-frequency = <16000000>;
+};
+
+&mmc0 {
+       fifo-mode;
+       max-frequency = <16000000>;
+};
+
+&mmc1 {
+       fifo-mode;
+       max-frequency = <16000000>;
+};
+
+&pinctrl {
+       bootph-pre-ram;
 };
 
 &timer3 {
-       compatible = "rockchip,rk3368-timer", "rockchip,rk3288-timer";
-       u-boot,dm-spl;
        clock-frequency = <24000000>;
+       bootph-pre-ram;
+};
+
+&uart2 {
+       bootph-pre-ram;
 };